scholarly journals Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

2021 ◽  
Vol 10 (6) ◽  
pp. 1-10
Author(s):  
S.C. Wagaj ◽  
◽  
S.C. Patil ◽  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Silicon On Insulator ◽  
Cmos Circuits ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
Junctionless Transistor ◽  
Dual Gate ◽  
Static Power

In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

scholarly journals Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology

2019 ◽  
Vol 14 (2) ◽  
pp. 912
Author(s):  
Woo Wei Kai ◽  
Nabihah Ahmad ◽  
Mohamad Hairol Jabbar
Keyword(s):  
Low Power ◽  
Average Power ◽  
Full Adder ◽  
Oxide Thickness ◽  
Low Complexity ◽  
Operating Voltage ◽  
Short Channel ◽  
Static Power ◽  
Subthreshold Leakage ◽  
Power Delay Product

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of  supply. The result showed the reduction of VBB technique in term of peak power,  and average power,   compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.

scholarly journals A Low-Power and In Situ Annealing Technique for the Recovery of Active Devices After Proton Irradiation

2018 ◽  
Vol 170 ◽  
pp. 01006 ◽  
Author(s):  
Laurent A. Francis ◽  
Amor Sedki ◽  
Nicolas André ◽  
Valéria Kilchytska ◽  
Pierre Gérard ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect Transistors ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
High Dose ◽  
Partial Recovery ◽  
Proton Radiation ◽  
Cmos Inverter ◽  
Inversion Point

In this paper, we study the recovery of onmembrane semiconductor components, such as N-type Field-Effect Transistors (FETs) available in two different channel widths and a Complementary Metal-Oxide-Semiconductor (CMOS) inverter, after the exposure to high dose of proton radiation. Due to the ionizing effect, the electrical characteristics of the components established remarkable shifts, where the threshold voltages showed an average shift of -480 mV and -280 mV respectively for 6 μm and 24 μm N-channel transistors, likewise the inversion point of the inverter showed an important shift of -690 mV. The recovery concept is based mainly on a micro-hotplate, fabricated with backside MEMS micromachining structure and a Silicon-On-Insulator (SOI) technology, ensuring rapid, low power and in situ annealing technique, this method proved its reliability in recent works. Annealing the N-channel transistors and the inverter for 16 min with a temperature of the heater up to 385 °C, guaranteed a partial recovery of the semiconductor based components with a maximum power consumption of 66 mW.

scholarly journals A Novel NOR-Type TCAM Deploy Dual-VT cell with OR-Type Cascade Match-Line Structure

2020 ◽  
Vol 9 (10) ◽  
pp. 35-39
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Clock Cycle ◽  
High Capacity ◽  
Cmos Technology ◽  
Stress Effect ◽  
Content Addressable Memory ◽  
Routing Table ◽  
Trade Offs ◽  
Static Power

We look over improvements in the schemes of large size content addressable memory (CAM). A CAM is a very important device that executes the routing table function within a single clock cycle in network router to transmit information over the network. CAMs are particularly popular in network switches to classify and sending information packets, they are also helpful in other different applications that require fast information retrieval from routing table. The primary CAM configuration challenge is to decrease power dissipation related with the lot of parallel activity in memory circuitry during search operation. As innovation going on in technology scaling, it continues minimizing the dynamic power dissipation of CAMs, however it also rises the leakage current of transistors. Thus, the static power is turning into a noteworthy bit of the whole power dissipation in CAMs. Here, we introduced a procedure which advantageous for high capacity Ternary Content Addressable Memory (TCAM) that minimize the static power dissipation in SRAM storage cell part and speed up activity in searching part of TCAM cell. We also divide whole memory into equivalent segments which improve performance of our design. We examine the different schemes and introduced the trade-offs of applying the techniques. Simulation and design have done by using Tanned EDA V.16 tool. For recreations of Low power TCAM structures we utilized predictive technology model (PTM) 45nm for high performance (HP) and low power (LP), which incorporate metal gate, high-k and stress effect of CMOS technology.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET For Low Power Applications

2021 ◽  
Author(s):  
Prashant Kumar ◽  
Munish Vashisht ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Future Generation ◽  
Threshold Current ◽  
Cmos Inverter ◽  
Drive Current ◽  
Subthreshold Current ◽  
Pmos Transistor ◽  
Good Agreement ◽  
The Ideal

Abstract Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET has been explored for low power applications. This paper presents an analytical model of subthreshold current of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET. The analytical results were compared with TMSG MOSFET and good agreement was obtained. The sub-threshold current of the device is very low and consider for the implementation of CMOS inverter. A PMOS transistor is designed and the drive current of the PMOS transistor is tuned with the NMOS device to obtain the ideal matching in the drive current. A CMOS inverter has been designed. The transient and DC behavior of the device have been examined. The power dissipation of the CMOS inverter has been computed and compared with CMOS DMG-SOI JLT inverter. The power dissipation is 5 times less in proposed device as compared to CMOS DMG-SOI JLT inverter. This exhibits an excellent improvement in power dissipation which is useful for making low power future generation devices.

HIGHLY SCALED CMOS DEVICE TECHNOLOGIES WITH NEW STRUCTURES AND NEW MATERIALS

2006 ◽  
Vol 16 (01) ◽  
pp. 147-173
Author(s):  
YANGYUAN WANG ◽  
RU HUANG ◽  
JINFENG KANG ◽  
SHENGDONG ZHANG
Keyword(s):  
Field Effect Transistors ◽  
Silicon Film ◽  
Double Gate ◽  
New Materials ◽  
Metal Gate ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
High K ◽  
Dual Metal

In this paper field effect transistors (FETs) with new materials and new structures are discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction between high quality high k material and low EOT, is investigated. EOT of the gate stack can be scaled down to 0.65nm for MOS capacitor and 0.95nm for MOSFET with higher carrier mobility. A new dual metal gate/high k CMOS integration process was demonstrated based on a dummy HfN technique for better high k quality and metal gate integration. Several new double gate FETs are proposed and investigated, including vertical double gate device with an asymmetric graded lightly doped drain (AGLDD) for better short channel behavior, self-aligned electrically separable double gate device for dynamic threshold voltage operation, new 3-D CMOS inverter based on double gate structure and SOI substrate for compact configuration and new full-symmetric DGJFET for 10nm era with greatly relaxed requirement of silicon film thickness and device design simplification.

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