scholarly journals Performance enhancement of GaSb vertical nanowire p-Type MOSFETs on Si by rapid thermal annealing

2021 ◽  
Author(s):  
Zhongyunshen Zhu ◽  
Johannes Svensson ◽  
Adam Jönsson ◽  
Lars Erik Wernersson
Keyword(s):  
Low Power ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Performance Enhancement ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
Stringent Requirement ◽  
Rf Applications ◽  
Low Power Logic ◽  
P Type

Abstract GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOSFETs, we have improved the average peak transconductance (g m,peak) by 50% among 28 devices and achieved 70 µS/µm at V DS = – 0.5 V in a device with 200-nm gate length. In addition, a low subthreshold swing down to 144 mV/dec as well as an off-current below 5 nA/µm which refers to the off-current specification in low-operation-power (LOP) condition has been obtained. Based on the statistical analysis, the results show a great enhancement in both on- and off-state performance with respect to previous work mainly due to the improved electrostatics and contacts after RTA, leading to a potential in low-power logic applications. We have also examined a short channel device with L g = 80 nm in RTA, which shows an increased gm,peak up to 149 µS/µm at V DS = – 0.5 V as well as a low on-resistance of 4.7 kΩ·µm. The potential of further enhancement in g m via RTA offer a good alternative to obtain high-performance devices for RF applications which have less stringent requirement for off-state performance. Our results indicate that post-fabrication annealing provides a great option to improve the performance of GaSb-based p-type devices with different structures for various applications.

Ultra-Shallow Junctions by Ion Implantation and Rapid Thermal Annealing: Spike-Anneals, Ramp Rate Effects

1999 ◽  
Vol 568 ◽  
Author(s):  
Aditya Agarwal ◽  
Hans-J. Gossmann ◽  
Anthony T. Fiory
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Driving Forces ◽  
Recent Experimental Data ◽  
Enhanced Diffusion ◽  
Temperature Ramp ◽  
Rate Effects ◽  
Low Energies ◽  
Ultra Shallow Junctions ◽  
P Type

ABSTRACTOver the last couple of years rapid thermal annealing (RTA) equipment suppliers have been aggressively developing lamp-based furnaces capable of achieving ramp-up rates on the order of hundreds of degrees per second. One of the driving forces for adopting such a strategy was the experimental demonstration of 30nm p-type junctions by employing a ramp-up rate of ≈400°C/s. It was subsequently proposed that the ultra-fast temperature ramp-up was suppressing transient enhanced diffusion (TED) of boron which results from the interaction of the implantation damage with the dopant. The capability to achieve very high temperature ramp-rates was thus embraced as an essential requirement of the next generation of RTA equipment.In this paper, recent experimental data examining the effect of the ramp-up rate during spike-and soak-anneals on enhanced diffusion and shallow junction formation is reviewed. The advantage of increasing the ramp-up rate is found to be largest for the shallowest, 0.5-keV, B implants. At such ultra-low energies (ULE) the advantage arises from a reduction of the total thermal budget. Simulations reveal that a point of diminishing return is quickly reached when increasing the ramp-up rate since the ramp-down rate is in practice limited. At energies where TED dominates, a high ramp-up rate is only effective in minimizing diffusion if the implanted dose is sufficiently small so that the TED can be run out during the ramp-up portion of the anneal; for larger doses, a high ramp-up rate only serves to postpone the TED to the ramp-down duration of the anneal. However, even when TED is minimized at higher implant energies via high ramp-up rates, the advantage is unobservable due to the rather large as-implanted depth. It appears then that while spike anneals allow the activation of ULE-implanted dopants to be maximized while minimizing their diffusion the limitation imposed by the ramp-down rate compromises the advantage of very aggressive ramp-up rates.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Rapid thermal annealing induced the c-axis (00 l) preferred orientation and the p-type thermoelectric properties of Bi-Sb-Te thin films

2020 ◽  
Vol 706 ◽  
pp. 138094 ◽  
Author(s):  
Athorn Vora–ud ◽  
Somporn Thaowonkaew ◽  
Jessada Khajonrit ◽  
Kunchit Singsoog ◽  
Pennapa Muthitamongkol ◽  
...  
Keyword(s):  
Thin Films ◽  
Thermal Annealing ◽  
Thermoelectric Properties ◽  
Rapid Thermal Annealing ◽  
Preferred Orientation ◽  
P Type

Rapid thermal annealing effects on the electrical, structural and morphological properties of Yb/p-type InP Schottky Structure

2015 ◽  
Vol 11 (1) ◽  
pp. 73-81 ◽  
Author(s):  
V. Rajagopal Reddy ◽  
D. Sri Silpa ◽  
V. Janardhanam ◽  
Hyung-Joong Yun ◽  
Chel-Jong Choi
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Morphological Properties ◽  
Annealing Effects ◽  
P Type ◽  
Schottky Structure

Supersaturated P-Type Polycrystaline Films Produced by Rapid Thermal Annealing of High Dose Boron Ion Implants for Interconnects and Shallow Junction Diffusion Sources

1990 ◽  
Vol 182 ◽  
Author(s):  
B. Raicu ◽  
M.I. Current ◽  
W.A. Keenan ◽  
D. Mordo ◽  
R. Brennan ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Thermal Annealing ◽  
Cross Section ◽  
Rapid Thermal Annealing ◽  
Single Crystal Silicon ◽  
High Dose ◽  
Crystal Silicon ◽  
Polysilicon Films ◽  
P Type

AbstractHighly conductive p+-polysilicon films were fabricated over Si(100) and SiO2 surfaces using high-dose ion implantation and rapid thermal annealing. Resistivities close to that of single crystal silicon were achieved. These films were characterized by a variety of electrical and optical techniques as well as SIMS and cross-section TEM.

scholarly journals A Study on the Chemistry of Epitaxial Ti3SiC2 Formation on 4H-SiC Using Al-Ti Annealing

2015 ◽  
Vol 821-823 ◽  
pp. 432-435 ◽  
Author(s):  
Tony Abi-Tannous ◽  
Maher Soueidan ◽  
Gabriel Ferro ◽  
Mihai Lazar ◽  
Berangère Toury ◽  
...  
Keyword(s):  
Magnetron Sputtering ◽  
Contact Resistance ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Specific Contact Resistance ◽  
Free Sample ◽  
Elemental Analyses ◽  
Specific Contact ◽  
P Type ◽  
Al Oxide

In order to form Ti3SiC2 on 4H-SiC(0001) 8°-off, 200 nm of Ti30Al70 was deposited onto SiC substrates by magnetron sputtering from pure Ti30Al70 targets. The samples were then annealed at 1000°C for 10 min under Ar atmosphere in a Rapid Thermal Annealing (RTA) furnace. Structural analyses reveal the formation of epitaxial hexagonal Ti3SiC2 (0001) oriented. Elemental analyses show that high amount of Al and O elements are present inside the deposit. Obviously, the formation of Ti3SiC2 is accompanied by parasitic Al oxide, probably due to some unwanted oxygen residual in the RTA chamber. By using proper backing steps before the annealing, the deposit is not anymore composed of only Ti3SiC2 but accompanied with other compounds (Al3Ti, and Al). On the oxide-free sample, the specific contact resistance ρc of the Ti3SiC2 based contact on p-type 4H-SiC (having Na= 2×1019 cm-3) was measured to be as low as 6×10-5 Ω.cm2.

Reversible p -type conductivity in H passivated nitrogen and phosphorous codoped ZnO thin films using rapid thermal annealing

2017 ◽  
Vol 400 ◽  
pp. 312-317 ◽  
Author(s):  
Ramanjaneyulu Mannam ◽  
E. Senthil Kumar ◽  
Nandita DasGupta ◽  
M.S. Ramachandra Rao
Keyword(s):  
Thin Films ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Zno Thin Films ◽  
Type Conductivity ◽  
P Type

The study of rapid thermal annealing on arsenic-doped ZnO for the p-type ZnO formation

2013 ◽  
Vol 362 ◽  
pp. 193-196 ◽  
Author(s):  
Yijia J. Chen ◽  
Hsin-Wei Jen ◽  
Ming-Show Wong ◽  
Ching-Hwa Ho ◽  
Jia-Hao Liang ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Doped Zno ◽  
P Type

Bandgap Shifting of an Ultra-Thin InGaAs/InP Quantum Well Infrared Photodetector via Rapid Thermal Annealing

1998 ◽  
Vol 525 ◽  
Author(s):  
D. K. Sengupta ◽  
S. Kim ◽  
H. C. Kuo ◽  
A. P. Curtis ◽  
K. C. Hsieh ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Spectral Response ◽  
Energy Levels ◽  
Blue Shift ◽  
Orbital Method ◽  
Quantum Well Infrared Photodetector ◽  
P Type ◽  
Anneal Time

ABSTRACTWe demonstrate that SiO2 cap rapid thermal annealing in ultra-thin p-type InGaAs/InP quantum wells can be used to produce large blue shifts of the band edge. A substantial bandgap blue shift, as much as 292.5 meV at 900°C has been measured and the value of the bandgap shift can be controlled by the anneal time. Theoretical modeling of the intermixing effect on the energy levels is performed based on the effective bond-orbital method, and we obtain a very good fit to the photoluminescence data. Compared to the as-grown detector, the peak spectral response of the annealed detector was shifted to longer wavelength without any major degradation in the responsivity characteristics.

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