scholarly journals Fabrication of encapsulated graphene-based heterostructure using molybdenum as edge-contacts

2021 ◽  
Vol 2145 (1) ◽  
pp. 012039
Author(s):  
Illias Klanurak ◽  
Kenji Watanabe ◽  
Takashi Taniguchi ◽  
Sojiphong Chatraphorn ◽  
Thiti Taychatanapat
Keyword(s):  
Contact Resistance ◽  
Quantum Transport ◽  
High Performance ◽  
Room Temperature ◽  
Ohmic Contacts ◽  
Hexagonal Boron Nitride ◽  
High Mobility ◽  
Thin Sheets ◽  
Adhesion Layer ◽  
Twisted Bilayer Graphene

Abstract Graphene is an intriguing platform to study exotic quantum transport phenomena due to its intrinsically high mobility and remarkable electronic properties. To achieve high-performance device, graphene is usually encapsulated between thin sheets of hexagonal boron nitride (hBN) to protect graphene layer from extrinsic impurities. Cr/Au is typically employed to make contacts with the edges of the heterostructure. In this research, Mo is used as an alternative electrode for graphene without adhesion layer to simplify the fabrication process. hBN-graphene-hBN heterostructures were fabricated by a pick-up technique and etched in O2/CHF3 gases to expose graphene edges. Mo contacts were deposited onto the substrates by sputtering. We achieved ohmic contacts between graphene and Mo. The contact resistance reaches the maximum of around 1,300 Ω·μm at charge neutrality point and decreases to 975 Ω·μm at the density of 4×1012 cm−2. We observed that the contact resistance increases over time likely due to the oxidation of Mo but remained ohmic after 2 months. The intrinsic transport characteristics of graphene can still be obtained by using four-probe measurement. Here, we realized a high-quality twisted bilayer graphene device with a room-temperature mobility of 27,000 cm2/V·s indicating that Mo can be used as edge-contacts to probe the transport properties of graphene.

Ni-Al-Ti Ohmic Contacts with Preserved Form Factor and Few 10- 4 Ωcm2 Specific Resistance on 0.1-1 Ωcm p-Type 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 385-388 ◽  
Author(s):  
Roberta Nipoti ◽  
Maurizio Puzzanghera ◽  
Maria Concetta Canino ◽  
Giovanna Sozzi ◽  
Paolo Fedeli
Keyword(s):  
Form Factor ◽  
Contact Resistance ◽  
Contact Area ◽  
Room Temperature ◽  
Ohmic Contacts ◽  
Specific Resistance ◽  
Thickness Ratio ◽  
Specific Contact Resistance ◽  
Specific Contact ◽  
P Type

This study shows that a thin Ni film on Al/Ti/4H-SiC metal pads allows to preserve the pad form factor during a 1000 °C/2 min treatment, provided that the Al and Ti film thicknesses are sufficiently thin. Moreover, by reducing the Al to Ti thickness ratio, droplet formation in the contact area is avoided and a mirror-like appearance is obtained. This optimal contact morphology corresponds to a specific contact resistance of few 10-4Ωcm2at room temperature on p-type 4H-SiC with resistivity in the range 0.1 – 1 Ωcm.

A ROOM TEMPERATURE BALLISTIC DEFLECTION TRANSISTOR FOR HIGH PERFORMANCE APPLICATIONS

2009 ◽  
Vol 19 (01) ◽  
pp. 23-31 ◽  
Author(s):  
QUENTIN DIDUCK ◽  
HIROSHI IRIE ◽  
MARTIN MARGALA
Keyword(s):  
High Performance ◽  
Room Temperature ◽  
Ballistic Transport ◽  
High Mobility ◽  
Mean Free Path ◽  
Material System ◽  
Novel Device ◽  
Ballistic Electron ◽  
Ballistic Deflection Transistor ◽  
Channel Separation

The Ballistic Deflection Transistor (BDT) is a novel device that is based upon an electron steering and a ballistic deflection effect. Composed of an InGaAs - InAlAs heterostructure on an InP substrate, this material system provides a large mean free path and high mobility to support ballistic transport at room temperature. The planar nature of the device enables a two step lithography process, as well, implies a very low capacitance design. This transistor is unique in that no doping junction or barrier structure is employed. Rather, the transistor utilizes a two-dimensional electron gas (2DEG) to achieve ballistic electron transport in a gated microstructure, combined with asymmetric geometrical deflection. Motivated by reduced transit times, the structure can be operated such that current never stops flowing, but rather is only directed toward one of two output drain terminals. The BDT is unique in that it possesses both a positive and negative transconductance region. Experimental measurements have indicated that the transconductance of the device increases with applied drain-source voltage. DC measurements of prototype devices have verified small signal voltage gains of over 150, with transconductance values from 45 to 130 mS/mm depending upon geometry and bias. Gate-channel separation is currently 80nm, and allows for higher transconductance through scaling. The six terminal device enables a normally differential mode of operation, and provides two drain outputs. These outputs, depending on gate bias, are either complementary or non-complementary. This facilitates a wide variety of circuit design techniques. Given the ultralow capacitive design, initial estimates of ft, for the device fabricated with a 430nm gate width, are over a THz.

TiW/TiWN/Pt Ohmic Contacts to n-Type 3C-SiC

2006 ◽  
Vol 911 ◽  
Author(s):  
Kirk Hofeling ◽  
Loren Rieth ◽  
Florian Solzbacher
Keyword(s):  
Contact Resistance ◽  
Room Temperature ◽  
Ohmic Contacts ◽  
Specific Contact Resistance ◽  
Test Duration ◽  
Capping Layer ◽  
Interface Reactions ◽  
Transmission Line Method ◽  
Specific Contact

AbstractTiW(40 nm)/TiWN(80 nm)/Pt(500nm) was investigated as a new high-temperature compatible contact stack to 3C-SiC for harsh environment applications. Performance of TiW/TiWN/Pt contacts deposited on unintentionally doped (8.85×1018 cm-3) 3C-SiC grown by LPCVD to a thickness of ~1μm on (100) Si are reported. The linear transmission line method was used to determine specific contact resistance (ρc) at room temperature and for long-term tests at 300 °C. As deposited contacts were Ohmic with a ρc range of 1×10-4 to 1×10-3 cm2. These contacts were annealed for five minutes in forming gas (8% H2 92% Ar), at temperatures from 450 to 950 °C and all retained Ohmic character. Annealing samples at 450, 550 and 950 °C decreased ρc while anneling between 650 and 850 °C generally increased ρc.Auger Electron Spectroscopy (AES) analysis was performed on a sample annealed at 750 °C. The as-received surface was composed of Si and O; after a brief sputter etch a characteristic Pt peak became visible and the O peak decreased substantially. Depth profiles detected Si throughout the Pt capping layer but not in the TiW layers. We suspect that Si diffuses from the SiC substrate into the Pt capping layer and surface Si also reacts with O2 to from an oxide. These reactions, in combination with incomplete SiC/TiW interface reactions, are suspected to cause the increase of ρc for samples annealed between 650 and 850 °C. Annealing at 950 °C gave the lowest contact resistance of 2.3×10-5. Long-term testing at 300 °C for 190 hours, in atmosphere, was performed on contacts annealed at 450 °C. When heated, the contacts initial ρc of 2.1×10-4 cm2 increased to ~4×10-3 cm2 which remained stable for the test duration. After long-term testing the sample ρc measured at room temperature decreased to 9.8×10-5 cm2.

Submicron Pseudomorphic Hemt’S Using Non-Alloyed Ohmic Contacts with Contrast Enhancement.

1990 ◽  
Vol 181 ◽  
Author(s):  
Ph. Jansen ◽  
W. De Raedt ◽  
M. Van Hove ◽  
R. Jonckheere ◽  
R. Pereira ◽  
...  
Keyword(s):  
Electron Beam ◽  
Contact Resistance ◽  
Electron Beam Lithography ◽  
High Performance ◽  
Ohmic Contacts ◽  
Sintering Temperature ◽  
Enhancement Mode ◽  
First Time ◽  
Lower Contact ◽  
Very High

ABSTRACTWe report for the first time the realization of submicron pseudomorphic Al.15, Ga.85As-In.20Ga.80As HEMT’s with non-alloyed Pd/Ge ohmic coi tacts. Best results of contact resistance were obtained at a sintering temperature of 340°C with values as low as 0.057 Ωmm. Enhanced contrast, needed for accurate alignment of the gate by electron-beam lithography, was obtained by using Pd/Ge/Ti/Pd and Pd/Ge/Ti/Pt metal sequences. These contacts exhibited even lower contact resistances than the standard Pd/Ge contacts. Although Pd/Ge/Ti/Pd exhibits good morphology, reaction is witnessed at the edges, reducing the accuracy of alignment.Processed enhancement mode devices exhibit maximum transconductances in excess of 520 mS/mm and currents of 300 mA/mm for 0.3 micron gatelength. This study shows that the contact resistance is no longer a restriction for obtaining very high transconductances in high performance devices.

Cubic AlGaN/GaN Hetero-Field Effect Transistors with Normally On and Normally Off Operation

2009 ◽  
Vol 1202 ◽  
Author(s):  
Donat J. As ◽  
Elena Tschumak ◽  
Florentina Niebelschüetz ◽  
W. Jatal ◽  
Joerg Pezoldt ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Carrier Concentration ◽  
Field Effect ◽  
Room Temperature ◽  
Ohmic Contacts ◽  
Field Effect Transistors ◽  
Gate Length ◽  
Dc Characteristics ◽  
Threshold Voltages ◽  
Source Voltage

AbstractNon-polar cubic AlGaN/GaN HFETs were grown by plasma assisted MBE on 3C-SiC substrates. Both normally-on and normally-off HFETs were fabricated using contact lithography. Our devices have a gate length of 2 μm, a gate width of 25 μm, and source-to-drain spacing of 8 μm. For the source and drain contacts the Al0.36Ga0.64N top layer was removed by reactive ion etching (RIE) with SiCl4 and Ti/Al/Ni/Au ohmic contacts were thermally evaporated. The gate metal was Pd/Ni/Au. At room temperature the DC-characteristics clearly demonstrate enhancement and depletion mode operation with threshold voltages of +0.7 V and −8.0 V, respectively. A transconductance of about 5 mS/mm was measured at a drain source voltage of 10 V for our cubic AlGaN/GaN HFETs, which is comparable to that observed in non-polar a-plane devices. From capacity voltage measurements a 2D carrier concentration of about 7×1012 cm-2 is estimated. The influence of source and drain contact resistance, leakage current through the gate contact and parallel conductivity in the underlaying GaN buffer are discussed.

scholarly journals Rectifying effect in high-performance ballistic diode bridge with a unique design for thermal energy harvesting

2021 ◽  
Author(s):  
Dinh Cong Nguyen ◽  
Minwook Kim ◽  
Muhammad Hussain ◽  
Van Huy Nguyen ◽  
Yeon-jae Lee ◽  
...  
Keyword(s):  
Thermal Energy ◽  
High Performance ◽  
Room Temperature ◽  
Hexagonal Boron Nitride ◽  
Electrical Energy ◽  
Mean Free Path ◽  
Thermal Excitation ◽  
Ballistic Regime ◽  
Johnson Noise ◽  
Ballistic Diode

Abstract The long mean free path close to a micrometer in encapsulated graphene enabled us to rectify currents ballistically at room temperature. In this study, we introduce a ballistic rectifier that resembles a diode bridge and is based on graphene encapsulated using hexagonal boron nitride. Our device’s asymmetric geometry combined with the exploitation of the ratcheting effect means that it can operate successfully and provides excellent performance. The device’s estimated responsivities at 38,000 V/W for holes and 23,000 V/W for electrons at room temperature, are among the highest values for a ballistic device reported to date. Due to the device’s zero threshold voltage, it is able to rectify Johnson noise signals converting thermal excitation to electrical energy at room temperature. The bandwidth of the device at the ballistic regime is estimated at ~ 1.1 GHz for holes and 2 GHz for electrons. The device developed in this study is an important step along an innovative pathway that will lead to harvesting electrical energy directly from thermal energy.

scholarly journals Amorphous NdIZO Thin Film Transistors with Contact-Resistance-Adjustable Cu S/D Electrodes

Membranes ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 337
Author(s):  
Xinyi Zhang ◽  
Kuankuan Lu ◽  
Zhuohui Xu ◽  
Honglong Ning ◽  
Zimian Lin ◽  
...  
Keyword(s):  
Thin Film ◽  
Contact Resistance ◽  
Thin Film Transistors ◽  
High Performance ◽  
Annealing Temperature ◽  
Orthogonal Design ◽  
High Mobility ◽  
Localized States ◽  
Oxide Semiconductor ◽  
Taguchi Orthogonal Design

High-performance amorphous oxide semiconductor thin film transistors (AOS-TFT) with copper (Cu) electrodes are of great significance for next-generation large-size, high-refresh rate and high-resolution panel display technology. In this work, using rare earth dopant, neodymium-doped indium-zinc-oxide (NdIZO) film was optimized as the active layer of TFT with Cu source and drain (S/D) electrodes. Under the guidance of the Taguchi orthogonal design method from Minitab software, the semiconductor characteristics were evaluated by microwave photoconductivity decay (μ-PCD) measurement. The results show that moderate oxygen concentration (~5%), low sputtering pressure (≤5 mTorr) and annealing temperature (≤300 °C) are conducive to reducing the shallow localized states of NdIZO film. The optimized annealing temperature of this device configuration is as low as 250 °C, and the contact resistance (RC) is modulated by gate voltage (VG) instead of a constant value when annealed at 300 °C. It is believed that the adjustable RC with VG is the key to keeping both high mobility and compensation of the threshold voltage (Vth). The optimal device performance was obtained at 250 °C with an Ion/Ioff ratio of 2.89 × 107, a saturation mobility (μsat) of 24.48 cm2/(V·s) and Vth of 2.32 V.

Optimizing n+ Ohmic Contacts on GaAs for HemtS

1992 ◽  
Vol 260 ◽  
Author(s):  
H. M. Harris ◽  
J. R. Farley
Keyword(s):  
Contact Resistance ◽  
Ohmic Contact ◽  
High Performance ◽  
Ohmic Contacts ◽  
Layer Structure ◽  
High Electron Mobility Transistor ◽  
High Electron ◽  
Alloy Process ◽  
Spacer Layer ◽  
Better Than

ABSTRACTLow ohmic contact resistance is essential for high performance microwave and millimeter wave transistors. Rapid thermal processing (RTP) has been used to optimize the ohmic contact resistance of gold - germanium / nickel / gold metallizations on gallium arsenide (GaAs) layers for high electron mobility transistor (HEMT) applications. A HEMT layer structure consisting of a 9000Å buffer layer grown on a semi-insulating substrate followed by a 20Å undoped AlGaAs spacer layer, a 700Å Al0.22Ga0.78 As layer doped at 1.0 × 1018cm-3and a 500Å GaAs cap layer doped at 1.5 × 1018 cm°C to 450°C. Time at temperature was varied from 10 seconds to 1 minute. Optimum conditions for our equipment and layer structure were found to be 365°C for 30 seconds. These conditions produced contact resistances of 0.08 ohm-mm (approximately 2.0 times better than the standard furnace alloy process).

Temperature Behavior of Pt/Au Ohmic Contacts to p-GaN

1997 ◽  
Vol 468 ◽  
Author(s):  
D. J. King ◽  
L. Zhang ◽  
J. C. Ramer ◽  
S. D. Hersee ◽  
L. F. Lester
Keyword(s):  
Contact Resistance ◽  
Room Temperature ◽  
Ohmic Contacts ◽  
Characteristic Curve ◽  
Specific Contact Resistance ◽  
Metal Contacts ◽  
Dopant Activation ◽  
Specific Contact ◽  
Order Of Magnitude ◽  
Increasing Temperature

ABSTRACTOhmic contacts to Mg-doped p-GaN grown by MOCVD [1] are studied using a circular transmission line model (TLM) to avoid the need for isolation. For samples which use a p-dopant activation anneal before metallization, no appreciable difference in the specific contact resistance, rc, as a function of different capping options is observed. However, a lower rc is obtained when no pre-metallization anneal is employed, and the post-metallization anneal simultaneously activates the p-dopant and anneals the contact. This trend is shown for Pt/Au, Pt, Pd/Pt/Au, and Ni/Au contacts to p-GaN. The rc 's for these metal contacts are in the range of 1.4–7.6 × 10-3 ohm-cm2 at room temperature at a bias of 10mA. No particular metallization formula clearly yields a consistently superior contact. Instead, the temperature of the contact has the strongest influence.Detailed studies of the electrical properties of the Pt/Au contacts reveal that the I-V linearity improves significantly with increasing temperature. At room temperature, a slightly rectified I-V characteristic curve is obtained, while at 200°C and above, the I-V curve is linear. For all the p-GaN samples, it is also found that the sheet resistance decreases by an order of magnitude with increasing temperature from 25°C to 350°C. The specific contact resistance is also found to decrease by nearly an order of magnitude for a temperature increase of the same range. A minimum rc of 4.2 × 10-4 ohm-cm2 was obtained at a temperature of 350°C for a Pt/Au contact. This result is the lowest reported rc for ohmic contacts to p-GaN.

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