scholarly journals Characterising the Performance of High-Speed Data Converters for RFSoC-based Radio Astronomy Receivers

2020 ◽  
Author(s):  
Chao Liu ◽  
Michael E Jones ◽  
Angela C Taylor
Keyword(s):  
Radio Astronomy ◽  
High Speed ◽  
Dynamic Range ◽  
Data Converters ◽  
Spurious Free Dynamic Range ◽  
High Speed Data ◽  
On Chip ◽  
Analogue To Digital ◽  
Adjacent Channels ◽  
Point Arithmetic

Abstract RF system-on-chip (RFSoC) devices provide the potential for implementing a complete radio astronomy receiver on a single board, but performance of the integrated analogue-to-digital converters is critical. We have evaluated the performance of the data converters in the Xilinx ZU28DR RFSoC, which are 12-bit, 8-fold interleaved converters with a maximum sample speed of 4.096 Giga-sample per second (GSPS). We measured the spurious-free dynamic range (SFDR), signal-to-noise and distortion (SINAD), effective number of bits (ENOB), intermodulation distortion (IMD) and cross-talk between adjacent channels over the bandwidth of 2.048 GHz. We both captured data for off-line analysis with floating-point arithmetic, and implemented a real-time integer arithmetic spectrometer on the RFSoC. The performance of the ADCs is sufficient for radio astronomy applications and close to the vendor specifications in most of the scenarios. We have carried out spectral integrations of up to 100 s and stability tests over tens of hours and find thermal noise-limited performance over these timescales.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

A High Linear CMOS Body Effect Compensation Bootstrapped Switch

2015 ◽  
Vol 24 (03) ◽  
pp. 1550032 ◽  
Author(s):  
Siwan Dong ◽  
Minjie Liu ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Body Effect ◽  
Spurious Free Dynamic Range ◽  
Source Voltage ◽  
Bootstrapped Switch ◽  
Free Dynamic ◽  
Better Than

This paper presents a new bootstrapped switch with high speed and low nonlinear distortion. Instead of fixed voltage, the gate-to-source voltage of switch varies with input to implement first-order body effect compensation. Post-layout simulations have been done in standard 0.18-μm CMOS process at 1.8 V, and results indicate that at 200 MHz sample rate, a peak signal-to-noise-and-distortion ratio (SNDR) of 98.4 dB, spurious-free dynamic range (SFDR) of 105.7 dB and total harmonic distortion (THD) of -104.9 dB can be acquired. For input frequency up to the 60 MHz frequency, proposed structure maintains |THD| over 85 dB, SFDR better than 86 dB, respectively.

scholarly journals 10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 563
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Communication Systems ◽  
Power Efficiency ◽  
High Speed ◽  
Closed Loop ◽  
Dynamic Range ◽  
Data Converters ◽  
Fully Differential ◽  
Biquad Filter ◽  
Bicmos Technology ◽  
Sige Bicmos

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations.

scholarly journals A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 507 ◽  
Author(s):  
Junjie Wu ◽  
Jianhui Wu
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Total Power ◽  
Measurement Results ◽  
Spurious Free Dynamic Range ◽  
Back Ground ◽  
Static Power ◽  
Asynchronous Sar ◽  
Analogue To Digital ◽  
Ground Calibration

A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm2. The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect to process-voltage-temperature (PVT). A background calibration of the inter-stage gain is proposed to adjust the inter-stage gain and to track the PVT variables. The measurement results show that, with calibration, the spurious-free-dynamic-range (SFDR) and signal-to-noise-and-distortion-ratio (SINAD) can be improved from 68 dB and 61 dB to 78 dB and 63 dB, respectively. The dynamic performance was stable under different VT conditions.

Sign in / Sign up

Export Citation Format

Share Document