scholarly journals A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 507 ◽  
Author(s):  
Junjie Wu ◽  
Jianhui Wu
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Total Power ◽  
Measurement Results ◽  
Spurious Free Dynamic Range ◽  
Back Ground ◽  
Static Power ◽  
Asynchronous Sar ◽  
Analogue To Digital ◽  
Ground Calibration

A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm2. The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect to process-voltage-temperature (PVT). A background calibration of the inter-stage gain is proposed to adjust the inter-stage gain and to track the PVT variables. The measurement results show that, with calibration, the spurious-free-dynamic-range (SFDR) and signal-to-noise-and-distortion-ratio (SINAD) can be improved from 68 dB and 61 dB to 78 dB and 63 dB, respectively. The dynamic performance was stable under different VT conditions.

scholarly journals A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 253
Author(s):  
Dong Wang ◽  
Jian Luan ◽  
Xuan Guo ◽  
Lei Zhou ◽  
Danyu Wu ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Open Loop ◽  
Total Power ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Self Calibration ◽  
Differential Nonlinearity ◽  
Bicmos Technology ◽  
Sige Bicmos

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

scholarly journals Effects of ADC Nonlinearity on the Spurious Dynamic Range Performance of Compressed Sensing

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Rongzong Kang ◽  
Pengwu Tian ◽  
Hongyi Yu
Keyword(s):  
Compressed Sensing ◽  
Dynamic Range ◽  
Dynamic Performance ◽  
Digital Converter ◽  
Analog To Digital ◽  
Sensing System ◽  
Spurious Free Dynamic Range ◽  
Simulation Results ◽  
The Impact ◽  
Free Dynamic

Analog-to-information converter (AIC) plays an important role in the compressed sensing system; it has the potential to significantly extend the capabilities of conventional analog-to-digital converter. This paper evaluates the impact of AIC nonlinearity on the dynamic performance in practical compressed sensing system, which included the nonlinearity introduced by quantization as well as the circuit non-ideality. It presents intuitive yet quantitative insights into the harmonics of quantization output of AIC, and the effect of other AIC nonlinearity on the spurious dynamic range (SFDR) performance is also analyzed. The analysis and simulation results demonstrated that, compared with conventional ADC-based system, the measurement process decorrelates the input signal and the quantization error and alleviate the effect of other decorrelates of AIC, which results in a dramatic increase in spurious free dynamic range (SFDR).

Design of Low Voltage Low Power ADC for WSN Node

2013 ◽  
Vol 760-762 ◽  
pp. 561-566
Author(s):  
Si Kui Ren ◽  
Zhi Qun Li
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Chip Area ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

scholarly journals Characterising the Performance of High-Speed Data Converters for RFSoC-based Radio Astronomy Receivers

2020 ◽  
Author(s):  
Chao Liu ◽  
Michael E Jones ◽  
Angela C Taylor
Keyword(s):  
Radio Astronomy ◽  
High Speed ◽  
Dynamic Range ◽  
Data Converters ◽  
Spurious Free Dynamic Range ◽  
High Speed Data ◽  
On Chip ◽  
Analogue To Digital ◽  
Adjacent Channels ◽  
Point Arithmetic

Abstract RF system-on-chip (RFSoC) devices provide the potential for implementing a complete radio astronomy receiver on a single board, but performance of the integrated analogue-to-digital converters is critical. We have evaluated the performance of the data converters in the Xilinx ZU28DR RFSoC, which are 12-bit, 8-fold interleaved converters with a maximum sample speed of 4.096 Giga-sample per second (GSPS). We measured the spurious-free dynamic range (SFDR), signal-to-noise and distortion (SINAD), effective number of bits (ENOB), intermodulation distortion (IMD) and cross-talk between adjacent channels over the bandwidth of 2.048 GHz. We both captured data for off-line analysis with floating-point arithmetic, and implemented a real-time integer arithmetic spectrometer on the RFSoC. The performance of the ADCs is sufficient for radio astronomy applications and close to the vendor specifications in most of the scenarios. We have carried out spectral integrations of up to 100 s and stability tests over tens of hours and find thermal noise-limited performance over these timescales.

Mitigating the Effects of Non-Linear Distortion Using Polarizers in Microwave Photonic Link

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Sarika Singh ◽  
Sandeep K. Arya ◽  
Shelly Singla
Keyword(s):  
Dynamic Range ◽  
Extinction Ratio ◽  
Polarization Angle ◽  
Third Order ◽  
Microwave Photonic ◽  
Linear Behavior ◽  
Spurious Free Dynamic Range ◽  
Non Linear ◽  
Intermodulation Distortions ◽  
Insertion Losses

AbstractA scheme to suppress nonlinear intermodulation distortion in microwave photonic (MWP) link is proposed by using polarizers to compensate inherent non-linear behavior of dual-electrode Mach-Zehnder modulator (DE-MZM). Insertion losses and extinction ratio have also been considered. Simulation results depict that spurious free dynamic range (SFDR) of proposed link reaches to 130.743 dB.Hz2/3. A suppression of 41 dB in third order intermodulation distortions and an improvement of 15.3 dB is reported when compared with the conventional link. In addition, an electrical spectrum at different polarization angles is extracted and 79^\circ is found to be optimum value of polarization angle.

scholarly journals Coulomb-actuated microbeams revisited: experimental and numerical modal decomposition of the saddle-node bifurcation

2021 ◽  
Vol 7 (1) ◽  
Author(s):  
Anton Melnikov ◽  
Hermann A. G. Schenk ◽  
Jorge M. Monsalve ◽  
Franziska Wall ◽  
Michael Stolz ◽  
...  
Keyword(s):  
Finite Element ◽  
Microelectromechanical Systems ◽  
Dynamic Range ◽  
Dynamic Performance ◽  
Major Step ◽  
Element Analysis ◽  
Electrostatic Actuators ◽  
Voltage Range ◽  
Drive Voltage ◽  
Depth Analysis

AbstractElectrostatic micromechanical actuators have numerous applications in science and technology. In many applications, they are operated in a narrow frequency range close to resonance and at a drive voltage of low variation. Recently, new applications, such as microelectromechanical systems (MEMS) microspeakers (µSpeakers), have emerged that require operation over a wide frequency and dynamic range. Simulating the dynamic performance under such circumstances is still highly cumbersome. State-of-the-art finite element analysis struggles with pull-in instability and does not deliver the necessary information about unstable equilibrium states accordingly. Convincing lumped-parameter models amenable to direct physical interpretation are missing. This inhibits the indispensable in-depth analysis of the dynamic stability of such systems. In this paper, we take a major step towards mending the situation. By combining the finite element method (FEM) with an arc-length solver, we obtain the full bifurcation diagram for electrostatic actuators based on prismatic Euler-Bernoulli beams. A subsequent modal analysis then shows that within very narrow error margins, it is exclusively the lowest Euler-Bernoulli eigenmode that dominates the beam physics over the entire relevant drive voltage range. An experiment directly recording the deflection profile of a MEMS microbeam is performed and confirms the numerical findings with astonishing precision. This enables modeling the system using a single spatial degree of freedom.

SFDR Improvement Algorithms for Current-Steering DACs

2015 ◽  
Vol 643 ◽  
pp. 101-108 ◽  
Author(s):  
Shaiful Nizam Mohyar ◽  
Masahiro Murakami ◽  
Atsushi Motozawa ◽  
Haruo Kobayashi ◽  
Osamu Kobayashi ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Weighted Averaging ◽  
Current Steering ◽  
Switching Sequence ◽  
Digital To Analog Converters ◽  
Compensation Methods ◽  
Spurious Free Dynamic Range ◽  
Data Weighted Averaging ◽  
Combined Algorithm

This paper presents algorithms for improving spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) — targeted at communication applications — by minimizing both current-source mismatches and glitches. Conventional segmented current-steering DACs suffer from static mismatches among current sources which cause nonlinearity and degrade SFDR, though glitch energy is relatively small. The data-weighted averaging (DWA) algorithm can reduce static current source mismatch effects, but it increases the effects of glitch energy. Here we investigate the use of both conventional Switching-Sequence Post-Adjustment (SSPA) calibration and One–Element-Shifting (OES) methods in order to reduce the effects of both nonlinearity and glitch energy. For further improvement, we propose and investigate a fully-digital combined algorithm to reduce static current source mismatch effects with minimal increase in the glitch energy. We also did simulations of the effect of combining these two compensation methods. Our MATLAB simulations show that the combined algorithm can improve SFDR performance by 24 dB, 22dB and 2dB compared to conventional thermometer-coded, one-element-shifting and SSPA methods respectively in some conditions. When we take current mismatch into account, the combined algorithm causes glitch energy to increase by only 0.02 to 0.2 % compared to the other three methods alone.

Large Spurious-free Dynamic Range RoF Link with Tunable CSR

2021 ◽  
Author(s):  
Ruiqiong Wang ◽  
Yangyu Fan ◽  
Jiajun Tan ◽  
Yongsheng Gao
Keyword(s):  
Dynamic Range ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic
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