A high-performance low-voltage current-mode min/max circuit

2015 ◽  
Vol 34 (4) ◽  
pp. 1172-1183 ◽  
Author(s):  
Reza Chavoshisani ◽  
Mohammad Hossein Moaiyeri ◽  
Omid Hashemipour
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Input Current ◽  
Efficient Design ◽  
Content Type ◽  
Current Comparator ◽  
Logic Module ◽  
Percent Improvement

Purpose – Current-mode approach promises faster and more precise comparators that lead to high-performance and accurate winner-take-all circuits. The purpose of this paper is to present a new high-performance, high-accuracy current-mode min/max circuit for low-voltage applications. In addition, the proposed circuit is designed based on a new efficient high-resolution current conveyor-based fully differential current comparator. Design/methodology/approach – The proposed design detects the min and max values of two analog current signals by means of a current comparator and a logic module. The comparator compares the values of the input current signals accurately and generates two digital control signals and the logic module determines the min and max values based on the controls signals. In addition, an accurate current copy module is utilized to copy the input current signals and convey them to the comparator and the logic module. Findings – The results of the comprehensive simulations, conducted using HSPICE with the TSMC 90 nm CMOS technology, demonstrate the high-performance and robust operation of the proposed design even in the presence of process, temperature, input current and supply voltage variations. For a case in point, for 5 μA differential input current the average propagation delay and power consumption of the proposed circuit are attained as 150 ps and 150 µW, respectively, which leads to more than 64 percent improvement in terms of power-delay product as compared with the most efficient design, previously presented in the literature. Originality/value – A new efficient structure for current-mode min-max circuit is proposed based on a novel current comparator design which is accurate, high-performance and robust to process, voltage and temperature variations.

An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter

2016 ◽  
Vol 25 (06) ◽  
pp. 1650066 ◽  
Author(s):  
Pantre Kompitaya ◽  
Khanittha Kaewdang
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Current Mode ◽  
Cmos Technology ◽  
Low Supply Voltage

A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18[Formula: see text][Formula: see text]m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

High-Performance Low Voltage Organic Thin-Film Transistors

2005 ◽  
Vol 870 ◽  
Author(s):  
Stijn De Vusser ◽  
Soeren Steudel ◽  
Kris Myny ◽  
Jan Genoe ◽  
Paul Heremans
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Organic Thin Film Transistors ◽  
Ring Oscillator ◽  
Ring Oscillators ◽  
Organic Thin Film ◽  
Supply Voltages

AbstractIn this work, we report on high-performance low voltage pentacene Organic Thin-Film Transistors (OTFT's) and circuits. Inverters and ring oscillators have been designed and fabricated. At 15 V supply voltage, we have observed invertors showing a voltage gain of 9 and an output swing of more than 13 V. As for the ring oscillators, oscillations started at supply voltages as low as 8.5 V. At a supply voltage of only 15 V, a stage delay time of 3.3 νs is calculated from experimental results.We believe that these results show for the first time a high speed ring oscillator at relatively low supply voltages. The required supply voltages can be obtained by rectification using an organic (pentacene) diode. These results may have an important impact on the realization of RF-ID tags: by integrating our circuits with an organic diode, the fabrication of organic RF-ID tags comes closer.

scholarly journals A design of low voltage OPAMP using split-length transistors

2014 ◽  
Vol 17 (1) ◽  
pp. 62-70
Author(s):  
Khanh Trung Le ◽  
Tu Trong Bui ◽  
Hung Duc Le ◽  
Kha Cong Pham
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Feedback Systems ◽  
Advanced Technique ◽  
Low Voltage Operation ◽  
Feedback Compensation ◽  
Indirect Feedback ◽  
Low Supply Voltage

In the paper, we present a design of a low voltage Operation Amplifier (OPAMP) circuit using split-length transistors. Indirect feedback compensation is an advanced technique used to stabilize the operation of an OPAMP. Cascode transistors are usually implemented for indirect feedback systems. However, these transistors are not suitable for low voltage design. In this study, we have taken advantage of split-length transistors and indirect feedback compensation technique to design a high performance OPAMP. As a result, the OPAMP operates not only at low supply voltage but also at high frequency. The OPAMP has been designed and fabricated in a 0.18um CMOS technology. This OPAMP achieves 100 dB gain, 90 MHz unity gain frequency and 60 degrees phase margin at 2 V supply voltage.

scholarly journals Current mode approach: High performance 0.35 μm CMOS class AB push-pull current amplifier

2003 ◽  
Vol 16 (2) ◽  
pp. 195-204
Author(s):  
Lyes Bouzerara ◽  
Mohand Belaroussi
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Current Mode ◽  
Current Gain ◽  
Design Parameters ◽  
Power Supply Voltage ◽  
Current Amplifier ◽  
Class Ab ◽  
Current Mirrors ◽  
General Circuits

A very high bandwidth class AB (Push-Pull) current amplifier using the compensation resistor technique is presented and analyzed. Such technique stands as a powerful method of bandwidth enhancement for general circuits using CMOS current mirrors. The proposed bandwidth is enhanced from 675 MHz for the uncompensated current amplifier to 745MHz for the compensated one without affecting the current gain and other design parameters such as power consumption and output swing. The circuit exhibits a current gain of 20 dB and consumes 1.48 mW for ?2.5V power supply voltage. All simulation results were performed using Hspice tool with 0.35^m CMOS TSMC parameters.

scholarly journals A low-voltage CMOS current-mode differential front-end for optical communications

2021 ◽  
Author(s):  
Bendong Sun
Keyword(s):  
Optical Communications ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Building Blocks ◽  
Switching Noise ◽  
Current Feedback ◽  
Fully Differential ◽  
Digital Circuitry

This thesis deals with the design of a low-voltage fully-differential CMOS current-mode preamplifier for optical communications. An in-depth comparative analysis of the building blocks of low-voltage CMOS current-mode circuits is carried out. Two new bandwidth enhancement techniques, namely inductor series-peaking and current feedback, are introduced and implemented in the design. The feedback also reduces the value of the series-peaking inductor. The minimum supply voltage of the amplifier is only one threshold voltage plus one pinch-off voltage. The preamplifier has a balanced differential topology such that the effect of bias dependent mismatches is minimized and the amplifier is insensitive to the switching noise caused by the digital circuitry. Negative differential current feedbacks are implemented to boost the bandwidth and increase the dynamic range.

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Abhay Sanjay Vidhyadharan ◽  
Sanjay Vidhyadharan
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Low Voltage ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Schmitt Trigger ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Requirement ◽  
Content Type

Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

A low-voltage, low-power voltage reference based on subthreshold MOSFETs

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740069 ◽  
Author(s):  
Liangwei Dong ◽  
Yueli Hu
Keyword(s):  
Low Power ◽  
Temperature Coefficient ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Channel Length ◽  
Voltage Reference ◽  
Single Chip ◽  
Low Power Cmos ◽  
Cmos Voltage Reference

A novel low-voltage low-power CMOS voltage reference independent of temperature is presented in this design. After considering the combined effect of (1) a perfect suppression of the temperature dependence of mobility; (2) the compensation of the channel length modulation effect on the temperature coefficient, a temperature coefficient of 10 ppm/[Formula: see text]C is achieved. Moreover, by adopting the subthreshold MOSFETs, there are no resistors used in the proposed structure. Therefore, the maximum supply current measured at the maximum supply voltage is 70 nA and at 80[Formula: see text]C. The circuit can be used as a voltage reference for high performance and low power dissipation on a single chip.

scholarly journals Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-18 ◽  
Author(s):  
Subodh Wairya ◽  
Rajendra Kumar Nagaria ◽  
Sudarshan Tiwari
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Vlsi Design ◽  
Reducing Power ◽  
Full Adder ◽  
Process Models ◽  
Majority Function ◽  
Simulation Results

This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 m process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

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