An efficient architecture for carry select adder

2017 ◽  
Vol 14 (3) ◽  
pp. 249-254 ◽  
Author(s):  
Vaithiyanathan Dhandapani
Keyword(s):  
Power Consumption ◽  
Large Scale ◽  
Vlsi Design ◽  
Vital Role ◽  
Portable Devices ◽  
Switching Activity ◽  
Content Type ◽  
Cell Library ◽  
Ripple Carry Adder ◽  
Carry Select Adder

Purpose Adders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, consequently, reduce power. Among these, modified CSLAs show a significant improvement, as they utilize a binary excess-1 code (BEC) to replace the add-one circuit. Design/methodology/approach This paper presents further enhancement in the modified CSLA by proposing a decision-based CSLA, which activates BEC on demand. This leads to reduced switching activity. The performance of the proposal is done by analyzing and comparing it with different adders. The comparison is done on the basis of three performance parameters: area, speed and power consumption. This is done by implementing the architecture on Xilinx Virtex5 XC5VLX30 in Verilog environment and is synthesized using Cadence® RTL Compiler® using TSMC 180-nm CMOS cell library. Findings Optimization of power, area and increasing the speed of operation are the three main areas of research in very-large-scale integration (VLSI) design for portable devices. As adders are the most fundamental units for any VLSI design, optimization at the adder level has a huge impact on the overall circuit. The modified CSLA has a BEC which continuously switches irrespective of the previous carry bit generated. The unwanted switching results in excess power consumption while also introducing additional delay. Hence, the author has proposed a decider circuit to avoid this excess switching activity. This allows switching of the BEC only when a previous carry is generated. The modified CSLA is based on the ripple carry adder, while the decider-based CSLA utilizes a carry look-ahead adder. This makes a decider-based CSLA faster while utilizing less area and power consumption when compared to the modified CSLA. Originality/value The efficiency of the proposed decider-based CSLA has been verified using Cadence RTL Compiler using TSMC 180-nm CMOS cell library and has been found to have 17 per cent power and 11.57 per cent area optimization when compared to the modified CSLA, while maintaining operating frequency.

scholarly journals Emerging trends in the developments of low power design technique

2020 ◽  
Vol 9 (3) ◽  
pp. 812
Author(s):  
Dimov Stojce Ilcev
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Large Scale ◽  
Vlsi Design ◽  
Low Power Design ◽  
Handheld Computers ◽  
Oxide Semiconductor ◽  
Battery Life ◽  
Portable Devices ◽  
Design Technique

In this paper is introduced a low power design technique for developing more reliable, functional, and more cost-effective handheld cellular telephones, portable computers, and peripherals. The portability requirements of handheld computers and other portable devices have placed tremendous pressure on electronic equipment designers, who need to deal with restrictions in the size of electronic units and power consumption. Even though battery technology is continuously improving, including reduced power consumption of processors and displays, extensive and continuous use of network services aggravates these issues. Now the onus is on the research and industrial communities to extend battery life and reduce weight. Equally, research on new techniques and technologies continues, to carefully manage energy consumption in mobile devices, while still providing continuous and fast connections to services and applications. This paper also discusses the novel trends in the developments and advancements in the area of low power Very Large Scale Integration (VLSI) design, dynamic power dissipation static power loss in Complementary Metal Oxide Semiconductor (CMOS), and advanced low power technique. Though low power as a well-established domain that undergone lots of developments from transistor sizing, process shrinkage, voltage scaling, clock gating, etc., to adiabatic logic are elaborated.  

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

Seoul and Tokyo will grow further apart

2018 ◽  
Keyword(s):  
South Korea ◽  
North Korea ◽  
Large Scale ◽  
Vital Role ◽  
Asia Pacific ◽  
Content Type ◽  
Psychological Issues ◽  
Security Issues ◽  
Will Force ◽  
Economic Ties

Subject Japan-South Korea relations. Significance Japan-South Korea relations have global significance. The two are East Asia’s largest and second-largest advanced economies and play a vital role in the economy of the Asia-Pacific region, including in the creation of large free trade areas. Their relationship also affects security issues related to North Korea. Impacts The shared threat from North Korea and the alliances both governments have with Washington will force a degree of cooperation. Intractable political and psychological issues related to history will impede cooperation indefinitely. Bilateral economic ties will remain large-scale and important for both sides, but gradually become less so.

Design of High-Speed Desensitized FIR Filter Employing Reduced Complexity SQRT Carry Select Adder

2019 ◽  
Vol 8 (10) ◽  
pp. 4288-4296
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Filter Design ◽  
Fir Filter ◽  
Simulation Tools ◽  
Booth Multiplier ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
Reduced Complexity ◽  
Fir Filter Design

In this research, a highly efficient desensitized FIR filter is designed to enhance the performance of digital filtering operation. With regard to FIR filter design, Multiplication and Accumulation component (MAC) forms the core processing entity. Half-band filters employing Ripple Carry Adder (RCA) based MAC structures have a sizeable number of logical elements, leading to high delay and high power consumption. To minimize these issues, a modified Booth multiplier encompassing SQRT Carry Select Adder (CSLA) based MAC component is proposed for the desensitized filter with reduced coefficients and employing lesser number of logical elements forgiving optimum performance with respect to delay and power consumption. The suggested FIR filter is simulated and assessed using EDA simulation tools from Modelsim 6.3c and Xilinx ISE. The results obtained from the proposed Desensitized FIR filter employing the modified booth multiplier with reduced complexity based SQRT CSLA show encouraging signs with respect to 12.08% reduction in delay and 2.2% reduction in power consumption when compared with traditional RCA based digital FIR filter.

scholarly journals COMPARISON AND ANALYSIS OF PERFORMANCE PARAMETERS OF BASIC ADDERS WITH SPARSE ADDER

2021 ◽  
Vol 6 (3) ◽  
Author(s):  
K Srivalli ◽  
Medha G H ◽  
Meghna K P ◽  
Mohan Kumar A ◽  
Darshan Halliyavar
Keyword(s):  
Large Scale ◽  
Vital Role ◽  
Performance Parameters ◽  
Look Ahead ◽  
Ripple Carry Adder ◽  
Large Scale Integration ◽  
Parallel Prefix ◽  
Scale Integration ◽  
Prefix Adder ◽  
Analysis Of Performance

Adders play a vital role in the design of a digital system using VLSI (Very Large Scale Integration) technique. Adders are the basic building block of ALU (Arithmetic Logic Unit) which is an important component of a processor. In this paper we are comparing and analyzing the performance parameters of basic adders like Ripple Carry Adder, Carry Select Adder, Carry Look Ahead Adder, Parallel Prefix Adder along with sparse adder. The above mentioned adders are implemented using 90nm technology in Xilinx ISE 14.7 Suite.

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

A NOVEL REGISTER-BINDING APPROACH TO REDUCE SPURIOUS SWITCHING ACTIVITY IN HIGH-LEVEL SYNTHESIS

2011 ◽  
Vol 20 (05) ◽  
pp. 943-973 ◽  
Author(s):  
ELIE ELAARAJ ◽  
IYAD OUAISS
Keyword(s):  
Power Consumption ◽  
Power Reduction ◽  
High Level Synthesis ◽  
Portable Devices ◽  
Switching Activity ◽  
Improve Performance ◽  
Main Design ◽  
Design And Optimization ◽  
High Level ◽  
Design Challenges

Optimizing area and timing have long been considered to be the main design challenges in high-level synthesis. A lot of research has been conducted in this area and many techniques to improve performance have been suggested. However, as design applications become more power-sensitive, and with the emergence of portable devices that operate under stringent power constraints, power consumption surfaced as a major issue to be considered in the design and optimization processes. This work studies the effects of binding and scheduling on power consumption in high-level synthesis by analyzing unnecessary switching. The major contribution of this work is to reduce the unnecessary switching at the inputs of a circuit's functional units, referred to as spurious switching activities. For this purpose, all spurious and nonspurious switching inputs in a circuit were identified, and many techniques were studied to find the optimal register bindings without inducing any increase in the number of storage elements. Power reduction was attained through altering register bindings using a cool-down simulated annealing approach. To test these techniques, a high-level synthesis environment, "Eridanus", was developed and several benchmarks, consisting of various complexities, have been tested. Using the approach suggested in this work, spurious switching activity was reduced by 40% on average.

scholarly journals Mission-driven arts organisations and initiatives

2019 ◽  
Vol 9 (2) ◽  
pp. 178-187
Author(s):  
Elizabeth Carnegie ◽  
Andreana Drencheva
Keyword(s):  
Large Scale ◽  
Special Section ◽  
Rapid Change ◽  
Vital Role ◽  
Content Type ◽  
Cultural Engagement ◽  
Work Arrangements ◽  
Multidimensional Uncertainty ◽  
Cultural Regeneration ◽  
Significant Point

Purpose The purpose of this paper is to examine how mission-driven arts organisations respond to the complex set of economic and social conditions that the authors here term as a significant point of rupture. Drawing on the papers that form a part of the special section of this issue, the authors critically examine how the intersection of globalisation and neoliberalism creates multidimensional uncertainty that shapes the opportunities, responsibilities, work arrangements, and lived experiences of artists and artist-led initiatives and organisations. Design/methodology/approach In this introduction to the symposium on mission-driven arts organisations and initiatives, the authors explore how the included articles question and introduce key concerns that govern, limit and support mission-driven arts organisations. Findings Drawing on the papers in this set, the authors note that mission-driven arts organisations are diverse and employ numerous organising forms. However, at their core is the pursuit of social objectives, which also requires the management of often conflicting artistic, economic, cultural and social demands. The authors explicate how mission-driven arts organisations respond to local agendas and work best at the community level. As such, they may not play a key role in tourism or large-scale cultural regeneration of spaces, but rather seek to make creative use of sunken and redundant, often inner city spaces to address local needs. Yet, the uncertainty that these organisations face shapes temporary solutions that may enhance the precariaty and pressures for artists and creative producers with likely impact on wellbeing. Originality/value This paper brings together original insights into how mission-drive organisations seek to overcome and indeed flourish in a time of rupture. It moves beyond the notion of cultural regeneration as an instrument of tourism, and tourism as a focus of regeneration, to consider the value such organisations bring to localities evidenced in both creative practices and as local cultural engagement beyond economic impact. In doing so, mission-driven arts organisations play a vital role in a time of rapid change.

scholarly journals An Efficient VLSI Design of 32X32 bit Multiplier using Wallace Tree Algorithm in Vivado HLS and Xilinx ISE Software using VHDL

2020 ◽  
Vol 9 (7) ◽  
pp. 490-495
Keyword(s):  
Power Dissipation ◽  
Circuit Complexity ◽  
Vlsi Design ◽  
Digital Signal ◽  
Major Drawback ◽  
Tree Algorithm ◽  
Wallace Tree ◽  
Look Ahead ◽  
Ripple Carry Adder ◽  
Carry Select Adder

Multiplier is the most basic component present in any digital system. These multipliers are mainly used in Digital Signal and Image Processing applications. In applications like image detection latest sophisticated algorithms like CNN are used which contains MAC units in their design. The multiplier used in MAC unit requires huge memory, offers high latency and consumes more power. There are many algorithms such as Combinational, Sequential and Array Multiplication Algorithms which helps in designing Multiplier. The major drawback in all designs is circuit complexity. The problem of latency and power dissipation are also present. Considering all the drawbacks present in those algorithms this paper proposes the usage of Wallace Tree Algorithm which consumes less power and has low latency. Also, there are many ways to add the final stage of partial products generated such as Carry Look Ahead adder, Carry Select Adder etc. This paper uses both Carry Select Adder and Ripple Carry Adder for performing final addition of partial products. All previous partial products are added using Half adders and Full adders. The Multiplier is designed using VHDL in Xilinx ISE and Vivado Platform.

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