Asymmetric Multilayered Gate Dielectric (AMGAD) surrounding gate MOSFET: A new structural concept for enhanced device performance

2008 ◽  
Author(s):  
H. Kaur ◽  
S. Kabra ◽  
S. Haldar ◽  
R.S. Gupta
Keyword(s):  
Gate Dielectric ◽  
Device Performance ◽  
Surrounding Gate ◽  
Structural Concept

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

2001 ◽  
Vol 78 (24) ◽  
pp. 3875-3877 ◽  
Author(s):  
H. N. Al-Shareef ◽  
A. Karamcheti ◽  
T. Y. Luo ◽  
G. Bersuker ◽  
G. A. Brown ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Device Performance ◽  
Remote Plasma ◽  
Plasma Nitridation

Optimization of Hafnium Zirconate (HfZrOx) Gate Dielectric for Device Performance and Reliability

2006 ◽  
Author(s):  
R. I. Hegde ◽  
D. H. Triyoso ◽  
S. Kalpat ◽  
S. B. Samavedam ◽  
J. K. Schaeffer ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Device Performance

Fundamental Narrow MOSFET Gate Dielectric Breakdown Behaviors and Their Impacts on Device Performance

2005 ◽  
Vol 52 (4) ◽  
pp. 473-483 ◽  
Author(s):  
C.H. Tung ◽  
K.L. Pey ◽  
L.J. Tang ◽  
Y. Cao ◽  
M.K. Radhakrishnan ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Device Performance

scholarly journals Study on the On/Off Ratio of the Cylindrical Surrounding Gate CNT Transistor Using Nonequlibrium Green’s Function Approach

2015 ◽  
Vol 7 (1-2) ◽  
pp. 11-21
Author(s):  
M. Munna ◽  
P. Das ◽  
M. F. Huq ◽  
I. Ahmed
Keyword(s):  
Gate Dielectric ◽  
Tight Binding ◽  
Gate Oxide ◽  
Channel Length ◽  
Current Ratio ◽  
Dielectric Thickness ◽  
Surrounding Gate ◽  
Contact Devices ◽  
Nanotube Transistors ◽  
Diameter Channel

The effects of the nanotube diameter, channel length, gate dielectric constant and gate dielectric thickness on the on-off current ratio performance of cylindrical surrounding gate carbon nanotube transistors are studied using a ?-orbital tight binding simulation model. The focus is both on Schottky-barrier and the doped source-drain contact devices. The on current significantly improves with high-? gate dielectric, whereas off current decreases. The device on-off current ratio improves, from 6.33 × 105 to 1.5 × 106 for doped contact and from 0.61 × 104 to 1.22 × 104 for SB device with thinner gate oxide. Minimum leakage current increases with larger diameter tube but on-current has no significant improvement. I-V characteristics are independent of channel length when it is larger than 15 nm. Significant increase in off-current occurs due to scaling the channel length down to 10 nm but on-off ratio still exceeds 103. In all cases, on-off ratio is higher and the effect of scaling is more prominent for doped contact devices than SB contact devices.

scholarly journals Solution Processed Low Voltage Metal-Oxide transistor by using TiO2 /Li-Al2O3 stacked Gate Dielectric

2021 ◽  
Author(s):  
Nila Pal ◽  
Utkarsh Pandey ◽  
Sajal Biring ◽  
Bhola Nath Pal
Keyword(s):  
Gate Dielectric ◽  
Low Voltage ◽  
Thin Film Transistor ◽  
Single Layer ◽  
Device Performance ◽  
Operating Voltage ◽  
Semiconductor Interface ◽  
Solution Processed ◽  
Bilayer Dielectric ◽  
Effective Carrier

Abstract A solution processed top-contact bottom gated SnO2 thin-film transistor (TFT) has been fabricated by using a TiO2/ Li-Al2O3 bilayer stacked gate dielectric that show operating voltage of this TFT within 2.0 V. It is observed that the bilayer dielectric has much higher areal capacitance with lower leakage current density that significantly improve the overall device performance of TFT. The TFT with bilayer gate dielectric shows an effective carrier mobility (µsat) of 9.2 cm2V− 1s− 1 with an on/off ratio of 7.1x103 which are significantly higher with respect to the TFT with a single layer Li-Al2O3 gate dielectric. The origin of this improvement is due to the Schottky junction between the highly doped silicon (p++-Si) and TiO2 of bilayer stacked dielectric that induced electrons to the channel which reduces the dielectric/semiconductor interface trap state. This investigation opens a new path to develop TFT device performance using a suitable bilayer stack of gate-dielectric.

Parylene copolymer gate dielectrics for organic field-effect transistors

2019 ◽  
Vol 7 (21) ◽  
pp. 6251-6256 ◽  
Author(s):  
Hyunjin Park ◽  
Jimin Kwon ◽  
Hyungju Ahn ◽  
Sungjune Jung
Keyword(s):  
Field Effect ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Operational Stability ◽  
Device Performance ◽  
Organic Field Effect Transistors

The parylene copolymer gate dielectric improves the device performance and operational stability without increasing fabrication complexity.

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