scholarly journals A gate-level leakage power reduction method for ultra-low-power CMOS circuits

2002 ◽  
Author(s):  
J.P. Halter ◽  
F.N. Najm
Keyword(s):  
Low Power ◽  
Reduction Method ◽  
Power Reduction ◽  
Leakage Power ◽  
Cmos Circuits ◽  
Ultra Low Power ◽  
Low Power Cmos

Single-event effects on ultra-low power CMOS circuits

2009 ◽  
Author(s):  
Megan C. Casey ◽  
Bharat L. Bhuva ◽  
Sarah A. Nation ◽  
Oluwole A. Amusan ◽  
T. Daniel Loveless ◽  
...  
Keyword(s):  
Low Power ◽  
Cmos Circuits ◽  
Single Event ◽  
Ultra Low Power ◽  
Single Event Effects ◽  
Low Power Cmos

Ultra low power CMOS circuits working in subthreshold regime for high temperature and radiation environments

2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000243-000250 ◽  
Author(s):  
E. Boufouss ◽  
L. A. Francis ◽  
P. Gérard ◽  
M. Assaad ◽  
D. Flandre
Keyword(s):  
High Temperature ◽  
Low Power ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Cmos Circuits ◽  
Detection Level ◽  
Ultra Low Power ◽  
Temperature Detection ◽  
Low Power Cmos ◽  
Soi Cmos

We present three ultra-low-power CMOS circuits: a temperature sensor, a voltage reference and a comparator developed for an ultra-low-power microsystem (ULP-MST) aiming at temperature sensing in harsh environments. The microsystem has 3 main functions: detecting a user-defined temperature threshold T0, generating a wake-up signal that turns on a data-acquisition microprocessor (located in a safe area) above T0, and measuring temperatures above T0. To achieve ultra-low-power operation, the three CMOS circuits are implemented in Silicon-on-Insulator (SOI) CMOS technology and are optimized to work in the subthreshold regime of the transistors. Since our application is mainly for harsh environment (i.e. high temperature and radiation), the chip has been designed using a suitable 1-μm SOI-CMOS technology. Simulations have been performed over the different process corners to verify functionality after fabrication. The typical power dissipation at high temperature (up to 240°C) is less than 100 μW at 5 V supply voltage. Measurements have validated correct operation in the temperature range from −40°C to 300°C before radiation and to 125°C after radiation up to now which will be extended further with a new set-up. Irradiation has been performed from 10 to 30 kGy. Such very high doses cause a shift down of output voltage values, which leads to a change of the temperature detection level and also increases the power dissipation by up to six times. Annealing effects help the partial recovery of the device operation at high temperature and the remote microprocessor enables calibration after radiation to readjust the temperature detection level.

An ultra-low-power CMOS voltage reference generator based on body bias technique

2013 ◽  
Vol 44 (12) ◽  
pp. 1145-1153 ◽  
Author(s):  
Yanhan Zeng ◽  
Yirong Huang ◽  
Yunling Luo ◽  
Hong-Zhou Tan
Keyword(s):  
Low Power ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Reference Generator ◽  
Low Power Cmos ◽  
Cmos Voltage Reference ◽  
Body Bias

scholarly journals Ultra-Low Power CMOS Readout for Resonant MEMS Strain Sensors

Proceedings ◽  
2018 ◽  
Vol 2 (13) ◽  
pp. 973
Author(s):  
Marco Crescentini ◽  
Cinzia Tamburini ◽  
Luca Belsito ◽  
Aldo Romani ◽  
Alberto Roncaglia ◽  
...  
Keyword(s):  
Low Power ◽  
Power Supply ◽  
First Generation ◽  
Negative Resistance ◽  
Low Noise ◽  
Strain Sensors ◽  
Current Conveyors ◽  
Ultra Low Power ◽  
Active Elements ◽  
Low Power Cmos

This paper presents an ultra-low power, silicon-integrated readout for resonant MEMS strain sensors. The analogue readout implements a negative-resistance amplifier based on first-generation current conveyors (CCI) that, thanks to the reduced number of active elements, targets both low-power and low-noise. A prototype of the circuit was implemented in a 0.18-µm technology occupying less than 0.4 mm2 and consuming only 9 µA from the 1.8-V power supply. The prototype was earliest tested by connecting it to a resonant MEMS strain resonator.

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