Flip-chip Packaging Configuration with Coplanar Strip Lines for Millimeter Electromagnetic Waves

2006 ◽  
Author(s):  
Y.K. Song ◽  
C.C. Lee
Keyword(s):  
Electromagnetic Waves ◽  
Flip Chip ◽  
Flip Chip Packaging ◽  
Millimeter Electromagnetic Waves ◽  
Strip Lines ◽  
Coplanar Strip Lines

Flip-Chip Interconnect for Coplanar Strip Lines

2008 ◽  
Vol 130 (4) ◽  
Author(s):  
Young K. Song ◽  
Chin C. Lee
Keyword(s):  
Flip Chip ◽  
Printed Circuit Boards ◽  
Equivalent Circuit Model ◽  
Parameter Analysis ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Full Wave ◽  
Solder Bumps ◽  
Strip Lines ◽  
Coplanar Strip Lines

A flip-chip interconnect configuration with coplanar strip (CPS) lines on printed circuit boards (PCBs) is reported for millimeter-wave applications. For CPS lines, the signal and ground electrodes both lie on the top surface of a chip or substrate. The flip-chip configuration was designed and implemented using a test chip on a dielectric board. Geometrical parameter analysis was carried out using full-wave simulation and equivalent circuit model for wideband performance. The chip was connected to the board using solder bumps. For a typical flip-chip assembly, the measured insertion loss is less than 3dB for frequencies of up to 35GHz and the return loss is higher than 15dB for frequencies of up to 29GHz using CPS flip-chip configuration.

A High-Linearity 76–85-GHz 16-Element 8-Transmit/8-Receive Phased-Array Chip With High Isolation and Flip-Chip Packaging

2014 ◽  
Vol 62 (10) ◽  
pp. 2337-2356 ◽  
Author(s):  
Bon-Hyun Ku ◽  
Ozgur Inac ◽  
Michael Chang ◽  
Hyun-Ho Yang ◽  
Gabriel M. Rebeiz
Keyword(s):  
Flip Chip ◽  
Phased Array ◽  
High Isolation ◽  
High Linearity ◽  
Flip Chip Packaging

Improved MEMS structure for stress-free flip-chip packaging

2009 ◽  
Vol 8 (2) ◽  
pp. 021118 ◽  
Author(s):  
Toshitsugu Ueda
Keyword(s):  
Flip Chip ◽  
Flip Chip Packaging

The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging

2011 ◽  
Vol 462-463 ◽  
pp. 1194-1199
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Process Time ◽  
Curing Process ◽  
Curing Time ◽  
Hold Temperature ◽  
Flip Chip Packaging ◽  
Time Cycle ◽  
The Impact

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.

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