Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which may compromise the life of flipchip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital Image Correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of a solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. As a specimen preparation for DIC technique, a flip-chip specimen was cross-sectioned before a manual polishing process followed by wet etching method in order to generate natural speckle patterns with high enough contrast on the measuring surface. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.