Solder Joint Reliability in Underfilled Flip Chip Package With a Consideration of Chip-Package-Interaction (CPI)

2011 ◽  
Author(s):  
Jae B. Kwak ◽  
Da Yu ◽  
Tung T. Nguyen ◽  
Seungbae Park
Keyword(s):  
Mechanical Behavior ◽  
Flip Chip ◽  
Thermal Loading ◽  
Solder Bump ◽  
Image Correlation ◽  
Specimen Preparation ◽  
Solder Bumps ◽  
Low K ◽  
Underfill Material ◽  
Dic Technique

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which may compromise the life of flipchip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital Image Correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of a solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. As a specimen preparation for DIC technique, a flip-chip specimen was cross-sectioned before a manual polishing process followed by wet etching method in order to generate natural speckle patterns with high enough contrast on the measuring surface. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

Deformation and Strain Measurement of Flip-Chip Solder Bump Under In-Situ Thermal Loading

2009 ◽  
Author(s):  
Jae B. Kwak ◽  
Dong Gun Lee ◽  
Tung Nguyen ◽  
Seungbae Park
Keyword(s):  
Deformation Behavior ◽  
Flip Chip ◽  
Thermal Loading ◽  
Solder Bump ◽  
Solder Joints ◽  
Image Correlation ◽  
Solder Bumps ◽  
Comparison Results ◽  
Dic Technique

Thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital Image Correlation (DIC) technique with optical microscope was adopted to quantify the deformation behavior and strains of a solder bump of flip-chip package subjected to thermal loading. A flip-chip specimen was cross-sectioned after manual polishing process followed by wet etching method in order to generate natural speckle patterns with high enough contrast on the measuring surface for employing DIC technique. The sample was placed in a miniature heating chamber and subjected to in-situ thermal loading from 25 °C to 100°C. During the heating, sequential microscopic images of the cross-sectioned surface of a solder bump were acquired, and the deformation behavior and strain distributions were successfully measured with submicron accuracy by applying DIC technique on the captured images. The computed full-field displacement fields clearly depicted both normal and shear deformation of the solder bump under the thermal loading. In addition, from the strain fields, it was observed that strains were mostly concentrated on the bottom portion of solder bump near the pad connected to substrate. In order to assess the thermo-mechanical strains of the flip-chip interconnections more quantitatively, the average strains of solder joints at different locations were also measured and compared to one another. By doing so, the strain trends of solder bumps were effectively analyzed with respect to the distance to neutral point (DNP). Finally, finite element analysis was conducted by simulating the thermal loading applied in the experiments, and comparison between the simulation and experimental results of displacements and strains was made. The comparison results exhibited satisfactory agreement, which ensured the validity of the experimental data and methodology. This study can further expedite the studies of electronic-package reliability through fatigue and crack failure analysis of the solder joints due to thermal cyclic loading.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

On the Multiscale Finite Element Analysis for Interfacial Fracture in Cu/Low-K Interconnects

2007 ◽  
Author(s):  
Tz-Cheng Chiu ◽  
Huang-Chun Lin
Keyword(s):  
Thin Film ◽  
Fracture Mechanics ◽  
Interface Crack ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Thermal Loading ◽  
Global Analysis ◽  
Crack Problem ◽  
Element Analysis ◽  
Low K

The interface crack problem in integrated circuit devices was considered by using global and local modeling approach. In the global analysis the thin film interconnect was modeled by a homogenized layer with material constants obtained from representative volume element (RVE) analysis. Local analyses were then considered to determine fracture mechanics parameters. It was shown that the multiscale model with RVE approach gives accurate fracture mechanics parameters for an interface crack under either thermal or mechanical loads; while significant error was observed when the thin film layers are ignored in the global analysis. The problem of an interface crack between low-k dielectric and etch-stop thin film in a flip-chip package under thermal loading was also investigated as an application example of the multiscale modeling.

A Theoretical Analysis of the Concept of Critical Clearance Toward a Design Methodology for the Flip-Chip Package

2007 ◽  
Vol 129 (4) ◽  
pp. 473-478 ◽  
Author(s):  
J. W. Wan ◽  
W. J. Zhang ◽  
D. J. Bergstrom
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Flow Characteristics ◽  
Quantitative Relation ◽  
Package Design ◽  
Solder Bumps ◽  
Filling Time ◽  
Encapsulation Process ◽  
Advanced Packaging ◽  
Gap Height

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon et al. (1999, “A Capillary-Driven Underfill Encapsulation Process,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

In‐Situ Mapping and Modeling Verification of Thermomechanical Deformation in Underfilled Flip‐Chip Packaging Using Moiré Interferometry

1996 ◽  
Vol 445 ◽  
Author(s):  
Xiang Dai ◽  
Connie Kim ◽  
Ralf Willecke ◽  
Paul S. Ho
Keyword(s):  
Flip Chip ◽  
Thermal Loading ◽  
Deformation Monitoring ◽  
Moiré Interferometry ◽  
Moire Interferometry ◽  
Fringe Analysis ◽  
Element Analysis ◽  
Solder Bumps ◽  
Thermomechanical Deformation

AbstractAn experimental technique of environmental moiré interferometry has been developed for in‐situ monitoring and analysis of thermomechanical deformation of microelectronics packages subjected to thermal loading under a controlled atmosphere. Coupled with fractional fringe analysis and digital image processing, the environmental moiré interferometry technique achieves accurate and realistic deformation monitoring with high sensitivity and excellent spatial resolution. It has been applied to investigate the thermomechanical deformations induced by thermal loading in an underfilled flip‐chip‐on‐board packaging. The effects of temperature change in the range of 102 °C to 22 °C are analyzed for underfill and solder bumps. In addition, shear deformation and shear strains across the solder bumps are determined as a function of temperature. The experimental results are compared with the results of a finite element analysis for modeling verification. Good agreement between the modeling results and experimental measurements has been found in the overall displacement fields. Through this study, the role of underfill in the thermomechanical deformation of the underfilled flip‐chip package is determined.

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