Modeling of Through-silicon Via (TSV) with an Embedded High-density Metal-insulator-metal (MIM) Capacitor

Author(s):  
Kyungjun Cho ◽  
Youngwoo Kim ◽  
Subm Kim ◽  
Gapyeol Park ◽  
Kyungjune Son ◽  
...  
2008 ◽  
Vol 93 (3) ◽  
pp. 033511 ◽  
Author(s):  
Yung-Hsien Wu ◽  
Chien-Kang Kao ◽  
Bo-Yu Chen ◽  
Yuan-Sheng Lin ◽  
Ming-Yen Li ◽  
...  

2007 ◽  
Vol 16 (9) ◽  
pp. 2803-2808 ◽  
Author(s):  
Ding Shi-Jin ◽  
Huang Yu-Jian ◽  
Huang Yue ◽  
Pan Shao-Hui ◽  
Zhang Wei ◽  
...  

2013 ◽  
Vol 2013 (1) ◽  
pp. 000794-000798
Author(s):  
C. Bunel ◽  
J-R. Tenailleau ◽  
F. Voiron ◽  
S. Borel ◽  
A. Lefevre

The 3D Silicon technology of IPDiA is a disruptive technology for miniaturization adopted by the best players in the Medical and Industrial segments for its outstanding performance and reliability demonstrated in harsh environments. The high density capacitors with multiple metal-insulator-metal (MIM) layer stacks in 3D structures reaching 250nF/mm2 already in production for several years is at the forefront of the research program where CEA-Leti and IPDiA are jointly providing innovative platforms for customers who want to combine these capacitors with Through Silicon Vias in order to demonstrate new technological concepts. The via last approach selected by IPDIA allows large possibility of integration combining TSV with active or passive devices such as High-density trench capacitors, MIM capacitors, Resistors, High-Q inductors or Zener diodes. In this paper, the interaction between TSV and IPD will be studied. Emphasis will be placed on the robustness of the 3D trench capacitor technology. Examples of applications using chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) will be illustrated.


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