A 1.25Gbps FPGA I/O Cell Design for Source-Synchronous System in 65nm CMOS Process

Author(s):  
Taotao Qian ◽  
Lei Chen ◽  
Jie Ni ◽  
Huabo Sun ◽  
Xuewu Li
2002 ◽  
Vol 748 ◽  
Author(s):  
R. Bruchhaus ◽  
T. Ozaki ◽  
U. Ellerkmann ◽  
J. Lian ◽  
Y. Kumura ◽  
...  

ABSTRACTFor high density FeRAM devices small cell sizes are essential. The combination of the capacitor on plug (COP) structure with the Chain FeRAM™ cell design is used to develop a 32Mb FeRAM. Based on a 0.2 μm standard CMOS process a silicide capped polysilicon plug is used to contact the bottom electrode of the ferroelectric capacitor to the transistor. The barrier contact to the plug is formed by IrO2/Ir and a sputter deposited PZT (40/60) is used as ferroelectric material. The function of SrRuO3 (SRO) layers at the electrode/PZT interfaces is described in more detail. Double sided SRO results in slightly lower coercive voltage and imprint behavior compared to capacitors without SRO. Double sided SRO is essential to achieve excellent fatigue behavior measured up to 1×1011 switching cycles.


Author(s):  
J. R. Sellar ◽  
J. M. Cowley

Current interest in high voltage electron microscopy, especially in the scanning mode, has prompted the development of a method for determining the contrast and resolution of images of specimens in controlled-atmosphere stages or open to the air, hydrated biological specimens being a good example. Such a method would be of use in the prediction of microscope performance and in the subsequent optimization of environmental cell design for given circumstances of accelerating voltage, cell gas pressure and constitution, and desired resolution.Fig. 1 depicts the alfresco cell of a focussed scanning transmission microscope with a layer of gas L (and possibly a thin window W) between the objective O and specimen T. Using the principle of reciprocity, it may be considered optically equivalent to a conventional transmission electron microscope, if the beams were reversed. The layer of gas or solid material after the specimen in the STEM or before the specimen in TEM has no great effect on resolution or contrast and so is ignored here.


1983 ◽  
Vol 44 (C3) ◽  
pp. C3-1195-C3-1199
Author(s):  
H. Anzai ◽  
T. Moriya ◽  
K. Nozaki ◽  
T. Ukachi ◽  
G. Saito

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.


2009 ◽  
Vol E92-C (2) ◽  
pp. 258-268 ◽  
Author(s):  
Ying-Zu LIN ◽  
Soon-Jyh CHANG ◽  
Yen-Ting LIU
Keyword(s):  

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