Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000698-000725 ◽  
Author(s):  
Kai Zoschke ◽  
Klaus-Dieter Lang
Keyword(s):  
Wafer Bonding ◽  
Rf Mems ◽  
Electrical Contacts ◽  
Bonding Process ◽  
Frame Structure ◽  
Back Side ◽  
Wafer Level ◽  
Free Standing ◽  
Carrier Wafer ◽  
Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

Temporary and permanent bonding enables 3D integration of ultrathin wafers

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001118-001144
Author(s):  
Elisabeth Brandl ◽  
Thomas Uhrmann ◽  
Mariana Pires ◽  
Stefan Jung ◽  
Jürgen Burggraf ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Bonding Process ◽  
Total Thickness ◽  
Wafer Level ◽  
3D Integration ◽  
Process Flow ◽  
Wafer Thickness ◽  
Temporary Bonding ◽  
Carrier Wafer ◽  
On Chip

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

scholarly journals Photonic Integration on the Hybrid Silicon Evanescent Device Platform

2008 ◽  
Vol 2008 ◽  
pp. 1-17 ◽  
Author(s):  
Hyundai Park ◽  
Alexander W. Fang ◽  
Di Liang ◽  
Ying-Hao Kuo ◽  
Hsu-Hao Chang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Wafer Bonding ◽  
Optical Gain ◽  
Hybrid Structure ◽  
Bonding Process ◽  
Wafer Level ◽  
Device Structure ◽  
Silicon Waveguides ◽  
Hybrid Silicon

This paper reviews the recent progress of hybrid silicon evanescent devices. The hybrid silicon evanescent device structure consists of III-V epitaxial layers transferred to silicon waveguides through a low-temperature wafer bonding process to achieve optical gain, absorption, and modulation efficiently on a silicon photonics platform. The low-temperature wafer bonding process enables fusion of two different material systems without degradation of material quality and is scalable to wafer-level bonding. Lasers, amplifiers, photodetectors, and modulators have been demonstrated with this hybrid structure and integration of these individual components for improved optical functionality is also presented. This approach provides a unique way to build photonic active devices on silicon and should allow application of silicon photonic integrated circuits to optical telecommunication and optical interconnects.

Glass-Glass Wafer Bonding for Microfluidic Devices

2008 ◽  
Author(s):  
Nick Aitken ◽  
Tony Rogers
Keyword(s):  
Wafer Bonding ◽  
Device Fabrication ◽  
Bonding Process ◽  
Glass Wafer ◽  
Wafer Level ◽  
Fluidic Devices ◽  
Polymer Devices ◽  
Acoustic Wave Device ◽  
Wave Device ◽  
Absorption Measurements

The AML AWB04 wafer bonding platform has been used to develop glass – glass bonding processes for both quartz and Pyrex substrates. This allows the accurate wafer to wafer alignment and bonding of two microfluidic (or any other glass device) wafers. In the case of Quartz, the process is also useful in the field of SAW (Surface Acoustic Wave) device fabrication. Although there are simpler and cheaper ways of creating micro fluidic devices (e.g adhesive bonded glass wafers, or all polymer devices), Pyrex is often required as the material is qualified for use in pharmaceutical and medical industries. The transmission properties of glass are also often needed where optical sensing and measurement is required. Pyrex is often needed for chemical compatibility, and is commonly used for glassware. Using the AML equipment, Pyrex and Quartz devices can be sealed at the wafer level with placement accuracies approaching ±1μm. The bonding process can also seal vacuum cavities, or seal controlled atmosphere cavities (e.g. reference cavities for optical absorption measurements). It is sometimes important to maintain precise glass micromachining dimensions and therefore it is necessary to bond at a temperature substantially less than the strain point of the glass: the AML equipment and processes can achieve this. The sealing strength is sufficient to withstand high pressure fluidic applications.

A Stamp-Sealed Microshell Package for RF MEMS Switches

2007 ◽  
Author(s):  
John Heck ◽  
Hanan Bar ◽  
Tsung-Kuan A. Chou ◽  
Quan Tran ◽  
Qing Ma ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Rf Mems ◽  
Mems Devices ◽  
Wafer Level ◽  
Subsequent Formation ◽  
Mems Switches ◽  
Mems Switch ◽  
Rf Mems Switches ◽  
Unique Method ◽  
Chemical Etchant

This paper describes a unique method of encapsulating MEMS switches at the wafer level using a thin-film “microshell” lid and a novel micro-embossing, or “stamping” technique to seal the lid. After fabrication of the MEMS switch and subsequent formation of the microshell, the switches are released through gold tunnels that allow the penetration of a chemical etchant. In a controlled ambient, a “stamp” wafer is aligned to the device wafer, and the wafers are thermally compressed together. This process applies pressure across each tunnel to fuse the gold, thereby sealing the microshell packages. By sealing and passivating the switches at the wafer level, the wafers can be exposed to backend processing, packaging, and assembly steps such as dicing without damaging the sensitive MEMS devices. Furthermore, the size, cost, and complexity of the packaged system are significantly reduced compared to standard wafer bonding processes.

Mechanics of Direct Wafer Bonding

2003 ◽  
Author(s):  
K. T. Turner ◽  
S. M. Spearing
Keyword(s):  
Wafer Bonding ◽  
Microelectromechanical Systems ◽  
Surface Condition ◽  
Bonding Process ◽  
Mems Devices ◽  
Wafer Level ◽  
Modeling Framework ◽  
Etch Patterns ◽  
Direct Wafer Bonding ◽  
Bonding Failure

Direct wafer bonding, also known as fusion bonding, has emerged as a key process in the manufacture of microelectromechanical systems (MEMS). The use of wafer bonding increases design flexibility, allows integration of dissimilar materials, and permits wafer-level packaging. While direct wafer bonding processes are becoming more prevalent in the fabrication of MEMS devices, failure during the bonding process is often a problem and is not completely understood. A modeling framework, based on the mechanics of the bonding process, has been on the mechanics of the bonding process, has been developed to correlate bonding failure to wafer geometry, surface condition, and etch patterns. The modeling approach is based on an energy balance between the reduction in surface energy as the bond is formed and the strain energy that is stored in the wafers as they conform to each other. The model allows the effect of flatness deviations, wafer geometry (i.e. thickness, diameter), wafer mounting, and etched features on the bonding process to be shown. Modeling results demonstrate that wafer bow, wafer thickness, and certain types of etch patterns are critical factors in controlling bonding success. Bonding experiments, in which specific flatness deviations and etch patterns have been introduced on wafers prior to bonding, have been carried out and compared to the modeling results. The understanding of the process gained through the modeling can be used to set tolerances on wafers, assist in mask layout, and guide the design of bonding equipment to ensure success in direct wafer bonding processes.

scholarly journals A Novel 3D Encapsulation Structure Based on Subwavelength Structure and Inserted Pyrex Glass for RF MEMS Infrared Detectors

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 974
Author(s):  
Jicong Zhao ◽  
Mingmin Ge ◽  
Chenguang Song ◽  
Ling Sun ◽  
Haiyan Sun
Keyword(s):  
Infrared Detectors ◽  
Rf Mems ◽  
Incident Angle ◽  
Incident Light ◽  
Electrical Contacts ◽  
Pyrex Glass ◽  
Wafer Level ◽  
Subwavelength Structure ◽  
Thermal Reliability ◽  
Maximum Transmission

A novel wafer-level three-dimensional (3D) encapsulation structure was designed for radio-frequency microelectromechanical system (RF MEMS) infrared detectors and investigated by using the finite element method (FEM) simulation. A subwavelength structure with a circular array of coaxial apertures was designed to obtain an extraordinary optical transmission (EOT) on top of a silicon substrate. For perpendicular incident light, a maximum transmission of 56% can be achieved in the long-wave infrared (LWIR) region and the transmission bandwidth covered almost the full LWIR region. Moreover, the maximum transmission could be further promoted with an increase in the incident angle. The vertical silicon vias, insulated by inserted Pyrex glass, were used to generate electrical contacts. With the optimized structure parameters, a feed-through level lower than −82 dB, and a transmission coefficient of one single via of more than −0.032 dB were obtained at a frequency from 0 to 2 GHz, which contributed to the low-loss transmission of the RF signals. Due to the matched thermal expansion coefficients (TECs) between silicon and Pyrex glass, the proposed via structure has excellent thermal reliability. Moreover, its thermal stress is much less than that of a conventional through-silicon via (TSV) structure. These calculated results demonstrate that the proposed 3D encapsulation structure shows enormous potential in RF MEMS infrared detector applications.

Effects of Bonding Process Parameters on Wafer-to-Wafer Alignment Accuracy in Benzocyclobutene (BCB) Dielectric Wafer Bonding

2005 ◽  
Vol 863 ◽  
Author(s):  
F. Niklaus ◽  
R.J. Kumar ◽  
J.J. McMahon ◽  
J. Yu ◽  
T. Matthias ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Layer Thickness ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Bonding Process ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
Bonding Parameters ◽  
Wafer Pair ◽  
The Impact

AbstractWafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential. In this paper we investigate the effects of thermal and mechanical bonding parameters on the achievable post-bonding wafer-to-wafer alignment accuracy for polymer wafer bonding with 200 mm diameter wafers. Our baseline wafer bonding process with softbaked BCB (∼35% cross-linked) has been modified to use partially cured (∼ 43% crosslinked) BCB. The partially cured BCB layer does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or slight shear forces at the bonding interface. As a result, the non-uniformity of the BCB layer thickness after wafer bonding is less than 0.5% of the nominal layer thickness and the wafer shift relative to each other during the wafer bonding process is less than 1 μm (average) for 200 mm diameter wafers. The critical adhesion energy of a bonded wafer pair with the partially cured BCB wafer bonding process is similar to that with soft-baked BCB.

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