Global Placement for Large-scale Mixed-size Design VLSI Circuits using Plant Model

2018 ◽  
Author(s):  
Prasun Datta ◽  
Shyamapada Mukherjee
Keyword(s):  
Large Scale ◽  
Vlsi Circuits ◽  
Plant Model ◽  
Global Placement

An Effective Cell Spreading Method for Force-Directed Global Placement

2014 ◽  
Vol 519-520 ◽  
pp. 911-918
Author(s):  
Xin Min Ma ◽  
Xu Qian ◽  
Wen Chao Gao
Keyword(s):  
Large Scale ◽  
Decisive Role ◽  
Cell Spreading ◽  
Fast Method ◽  
Wire Length ◽  
Additional Force ◽  
Large Scale Integration ◽  
Initial Placement ◽  
Scale Integration ◽  
Global Placement

Force-directed placement method for large scale integration physical design is a very effective and fast method to spread the cell uniformly in the placement region. But this kind of method also create large amount of cell overlap in initial placement. In this paper, we present an effective method to cope with cell spreading and add additional force without damaging the wire length. It mainly takes the following method: Firstly, in the prior period of iteration n we keep limit the cell moving distance using a rectangle structure .Because the prior iteration play a decisive role in the final placement quality. Secondly, after the cell relative order determined we can use a new method to compute the weight of additional force to accelerate converge. Thirdly, a strategy called iterative local refinement is added in the well-distributed placement to further reduce the total wire length.

Active power regulation for large-scale wind farms through an efficient power plant model of electric vehicles

2017 ◽  
Vol 185 ◽  
pp. 1673-1683 ◽  
Author(s):  
Mingshen Wang ◽  
Yunfei Mu ◽  
Hongjie Jia ◽  
Jianzhong Wu ◽  
Xiaodan Yu ◽  
...  
Keyword(s):  
Power Plant ◽  
Electric Vehicles ◽  
Large Scale ◽  
Wind Farms ◽  
Active Power ◽  
Plant Model ◽  
Power Regulation ◽  
Efficient Power

scholarly journals Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4771
Author(s):  
Hyunyul Lim ◽  
Minho Cheong ◽  
Sungho Kang
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Wireless Sensor ◽  
Large Scale Integration ◽  
Diagnosis Method ◽  
Diagnosis Accuracy ◽  
Scan Chain ◽  
Scale Integration

Scan structures, which are widely used in cryptographic circuits for wireless sensor networks applications, are essential for testing very-large-scale integration (VLSI) circuits. Faults in cryptographic circuits can be effectively screened out by improving testability and test coverage using a scan structure. Additionally, scan testing contributes to yield improvement by identifying fault locations. However, faults in circuits cannot be tested when a fault occurs in the scan structure. Moreover, various defects occurring early in the manufacturing process are expressed as faults of scan chains. Therefore, scan-chain diagnosis is crucial. However, it is difficult to obtain a sufficiently high diagnosis resolution and accuracy through the conventional scan-chain diagnosis. Therefore, this article proposes a novel scan-chain diagnosis method using regression and fan-in and fan-out filters that require shorter training and diagnosis times than existing scan-chain diagnoses do. The fan-in and fan-out filters, generated using a circuit logic structure, can highlight important features and remove unnecessary features from raw failure vectors, thereby converting the raw failure vectors to fan-in and fan-out vectors without compromising the diagnosis accuracy. Experimental results confirm that the proposed scan-chain-diagnosis method can efficiently provide higher resolutions and accuracies with shorter training and diagnosis times.

scholarly journals Recent Subthreshold Design Techniques

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Mohsen Radfar ◽  
Kriyang Shah ◽  
Jugdutt Singh
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Digital Design ◽  
Future Directions ◽  
Significant Development ◽  
Rapid Pace ◽  
Catch Up ◽  
Subthreshold Design

Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.

Skill Needs in VLSI Circuits

1992 ◽  
Vol 6 (1) ◽  
pp. 50-50
Author(s):  
Klaus Wölcken
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Vlsi Design ◽  
Vlsi Circuits ◽  
Academic Institutions ◽  
Directorate General

The forecast need for designers of Very Large Scale Integrated Circuits is described. The article then goes on to outline the support being provided for academic institutions involved with VLSI design training by the European Commission's Directorate General XIII.

scholarly journals Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

2021 ◽  
Vol 9 (VI) ◽  
pp. 962-966
Author(s):  
Ayush Tiwari
Keyword(s):  
Large Scale ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Time Duration ◽  
Leakage Reduction ◽  
Large Scale Integration ◽  
Cmos Vlsi ◽  
Scale Integration

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

Contact Resistance and Methods for its Determination

1982 ◽  
Vol 18 ◽  
Author(s):  
S. Simon Cohen
Keyword(s):  
Integrated Circuits ◽  
Contact Resistance ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Vlsi Circuits ◽  
Single Element ◽  
Large Scale Integration ◽  
Proper Definition ◽  
Definition Of ◽  
Scale Integration

The problem of low resistance ohmic contacts to silicon has been of considerable technological interest. In recent years this problem has received special attention owing to the effect of scaling in very-large-scale integration (VLSI) technology. The field of ohmic contacts to semiconductors comprises two independent parts. First there exists the material science aspect. The choice of a suitable metallization system, the proper semiconductor parameters and the method of the contact formation is not obvious. Then there is the question of the proper definition of the contact resistance and the way it is measured.Several methods for contact resistance determination have been introduced in the past. All seem to have some drawbacks that either limit their usefulness or raise doubts as to their validity in certain situations. We shall discuss the two-, three- and four-terminal resistor methods of measurement. Relevant theoretical considerations will also be included.For conventional integrated circuits with a moderate junction depth of 1–2 μm, aluminum is uniquely suited as a single-element metallization system. However, for VLSI applications it may become obsolete because of several well-defined metallurgical problems. Thus, other metallization systems have to be investigated. We shall briefly discuss some recent data on several other metallization systems. Finally, the problem of size effects on the contact resistance will be discussed. Recent experimental results suggest important clues regarding the development of alternative metallization systems for VLSI circuits and also point to revisions of estimates of achievable design rules.

Alignment mark materials for projection electron lithography

1994 ◽  
Vol 52 ◽  
pp. 712-713
Author(s):  
R. C. Farrow ◽  
J. A. Liddle ◽  
S. D. Berger ◽  
H. A. Huggins ◽  
J. S. Kraus ◽  
...  
Keyword(s):  
Large Scale ◽  
Vlsi Circuits ◽  
Detection Accuracy ◽  
Detection Scheme ◽  
Quantitative Measurements ◽  
Correct Alignment ◽  
Alignment Mark ◽  
Materials Used ◽  
Electron Lithography ◽  
Better Than

Recent advances in projection electron lithography have led to the development of a non-imaging mark detection scheme for alignment and registration that uses backscatter electron (BSE) contrast. The detection scheme is referred to as the beamlet method and uses the measured BSE emission to detect the correct alignment condition when the image of a mask mark is scanned over a corresponding wafer mark When applied to a SCALPEL system (i.e. SCattering with Angular Limitation in Projection Electron Lithography) mark detection accuracy of better than 10 nm has been reported. Incident electrons with approximately 100 keV energy will be used in a practical SCALPEL lithography tool. In this study we compare theoretical BSE ratios with quantitative measurements in a prototype SCALPEL machine. From these results we are able to predict the suitability of materials used for conductive links in very large scale integrated (VLSI) circuits.The theory for BSE emission from thin deposited films has been developed from work on thin self supporting films.

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