scholarly journals Recent Subthreshold Design Techniques

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Mohsen Radfar ◽  
Kriyang Shah ◽  
Jugdutt Singh
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Digital Design ◽  
Future Directions ◽  
Significant Development ◽  
Rapid Pace ◽  
Catch Up ◽  
Subthreshold Design

Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.

Design and Analysis of Multiple Parameters Optimized n-Bit Reversible Magnitude Comparators

2016 ◽  
Vol 25 (09) ◽  
pp. 1650112
Author(s):  
A. N. Nagamani ◽  
S. Ashwin ◽  
B. Abhishek ◽  
K. V. Arjun ◽  
V. K. Agrawal
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
State Of The Art ◽  
Digital System ◽  
Digital Design ◽  
Quantum Cost ◽  
Multiple Parameters ◽  
Digital System Design ◽  
Ancilla Inputs ◽  
Reversible Comparator

Reversible logic has gained its importance in the field of low power digital design. In any digital system, the comparator plays an important role in determining whether the two referenced numbers are either equal, greater or lesser. This work deals with optimization of existing reversible comparator designs and also proposes a new multiplexer-based logic for the design of reversible comparator along with design methodology for [Formula: see text]-bit comparators. The proposed design is optimized for multiple performance parameters compared to the existing state-of-the-art designs. The proposed multiplexer-based design has 51.9% improvement in quantum cost, 50% in garbage outputs and 62% in ancilla inputs. These optimized designs find application predominantly in the field of quantum computing for low power signal processing, parallel computing, memories, digital system design and multi-processing.

High Stable and Low Power 10T CNTFET SRAM Cell

2019 ◽  
Vol 29 (10) ◽  
pp. 2050158
Author(s):  
M. Elangovan ◽  
K. Gunavathi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Large Scale ◽  
Supply Voltage ◽  
Memory Cell ◽  
Vlsi Circuits ◽  
Order Effects ◽  
Power Performance ◽  
Sram Cell ◽  
Nanoscale Range

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

scholarly journals The Backpropagation Algorithm Implemented on Spiking Neuromorphic Hardware

2021 ◽  
Author(s):  
Alpha Renner ◽  
Forrest Sheldon ◽  
Anatoly Zlotnik ◽  
Louis Tao ◽  
Andrew Sornborger
Keyword(s):  
Machine Learning ◽  
Deep Learning ◽  
Low Power ◽  
Large Scale ◽  
Learning Algorithms ◽  
Vlsi Circuits ◽  
Machine Learning Algorithms ◽  
Backpropagation Algorithm ◽  
Neuromorphic Hardware ◽  
On Chip

Abstract The capabilities of natural neural systems have inspired new generations of machine learning algorithms as well as neuromorphic very large-scale integrated (VLSI) circuits capable of fast, low-power information processing. However, it has been argued that most modern machine learning algorithms are not neurophysiologically plausible. In particular, the workhorse of modern deep learning, the backpropagation algorithm, has proven difficult to translate to neuromorphic hardware. In this study, we present a neuromorphic, spiking backpropagation algorithm based on synfire-gated dynamical information coordination and processing, implemented on Intel's Loihi neuromorphic research processor. We demonstrate a proof-of-principle three-layer circuit that learns to classify digits from the MNIST dataset. To our knowledge, this is the first work to show a Spiking Neural Network (SNN) implementation of the backpropagation algorithm that is fully on-chip, without a computer in the loop. It is competitive in accuracy with off-chip trained SNNs and achieves an energy-delay product suitable for edge computing. This implementation shows a path for using in-memory, massively parallel neuromorphic processors for low-power, low-latency implementation of modern deep learning applications.

Case Study

2016 ◽  
pp. 283-322
Author(s):  
Martha Salome Lopez
Keyword(s):  
Low Power ◽  
Performance Optimization ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Electric Signal ◽  
Portable Devices ◽  
Frequency Synthesis ◽  
Research Fields ◽  
Large Scale Integration ◽  
Definition Of

Integrated circuits have been predominantly designed and developed by large firms and manufacturers; nowadays, any electronic engineer should be able to develop specific and innovative low-power designs using available open cores. This chapter presents the design process for a specific chip, beginning with a definition of its function, design considerations, power analysis, performance optimization, and chip optimization. The hardware and software for this circuit were developed for low-power implementation: it includes a processor, memory blocks, ports, buses, and a proposed application program, so it can be used as a starting point for other low-power very-large-scale integration (VLSI) circuits. The chip uses frequency synthesis and configuration parameters to deliver electric signals on a variety of waveforms and patterns. This design can be used in many research fields and application areas, where experiments or portable devices need low-power, programmable, and configurable electric signal generators.

scholarly journals Stator Non-Uniform Radial Ventilation Design Methodology for a 15 MW Turbo-Synchronous Generator Based on Single Ventilation Duct Subsystem

Energies ◽  
2021 ◽  
Vol 14 (10) ◽  
pp. 2760
Author(s):  
Ruiye Li ◽  
Peng Cheng ◽  
Hai Lan ◽  
Weili Li ◽  
David Gerada ◽  
...  
Keyword(s):  
Finite Element ◽  
Temperature Distribution ◽  
Design Methodology ◽  
Large Scale ◽  
Synchronous Generator ◽  
Axial Direction ◽  
Scale Model ◽  
Element Analysis ◽  
Axial Temperature ◽  
Ventilation Duct

Within large turboalternators, the excessive local temperatures and spatially distributed temperature differences can accelerate the deterioration of electrical insulation as well as lead to deformation of components, which may cause major machine malfunctions. In order to homogenise the stator axial temperature distribution whilst reducing the maximum stator temperature, this paper presents a novel non-uniform radial ventilation ducts design methodology. To reduce the huge computational costs resulting from the large-scale model, the stator is decomposed into several single ventilation duct subsystems (SVDSs) along the axial direction, with each SVDS connected in series with the medium of the air gap flow rate. The calculation of electromagnetic and thermal performances within SVDS are completed by finite element method (FEM) and computational fluid dynamics (CFD), respectively. To improve the optimization efficiency, the radial basis function neural network (RBFNN) model is employed to approximate the finite element analysis, while the novel isometric sampling method (ISM) is designed to trade off the cost and accuracy of the process. It is found that the proposed methodology can provide optimal design schemes of SVDS with uniform axial temperature distribution, and the needed computation cost is markedly reduced. Finally, results based on a 15 MW turboalternator show that the peak temperature can be reduced by 7.3 ∘C (6.4%). The proposed methodology can be applied for the design and optimisation of electromagnetic-thermal coupling of other electrical machines with long axial dimensions.

scholarly journals A Survey on Contrastive Self-Supervised Learning

Technologies ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 2
Author(s):  
Ashish Jaiswal ◽  
Ashwin Ramesh Babu ◽  
Mohammad Zaki Zadeh ◽  
Debapriya Banerjee ◽  
Fillia Makedon
Keyword(s):  
Computer Vision ◽  
Supervised Learning ◽  
Language Processing ◽  
Large Scale ◽  
Performance Comparison ◽  
Extensive Review ◽  
Future Directions ◽  
Dominant Component ◽  
Supervised Methods ◽  
The Cost

Self-supervised learning has gained popularity because of its ability to avoid the cost of annotating large-scale datasets. It is capable of adopting self-defined pseudolabels as supervision and use the learned representations for several downstream tasks. Specifically, contrastive learning has recently become a dominant component in self-supervised learning for computer vision, natural language processing (NLP), and other domains. It aims at embedding augmented versions of the same sample close to each other while trying to push away embeddings from different samples. This paper provides an extensive review of self-supervised methods that follow the contrastive approach. The work explains commonly used pretext tasks in a contrastive learning setup, followed by different architectures that have been proposed so far. Next, we present a performance comparison of different methods for multiple downstream tasks such as image classification, object detection, and action recognition. Finally, we conclude with the limitations of the current methods and the need for further techniques and future directions to make meaningful progress.

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

Design methodology for mass transfer-enhanced large-scale electrochemical reactor for CO2 reduction

2021 ◽  
pp. 130265
Author(s):  
Byungchan Jung ◽  
Seongho Park ◽  
Chulwan Lim ◽  
Woonghee Lee ◽  
Youngsub Lim ◽  
...  
Keyword(s):  
Mass Transfer ◽  
Design Methodology ◽  
Large Scale ◽  
Co2 Reduction ◽  
Electrochemical Reactor

scholarly journals Genetic and Transcriptomic Biomarkers in Neurodegenerative Diseases: Current Situation and the Road Ahead

Cells ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 1030
Author(s):  
Julie Lake ◽  
Catherine S. Storm ◽  
Mary B. Makarious ◽  
Sara Bandres-Ciga
Keyword(s):  
Neurodegenerative Diseases ◽  
Large Scale ◽  
Disease Diagnosis ◽  
Open Science ◽  
Future Directions ◽  
The Road ◽  
Current State ◽  
Molecular Complexity ◽  
Science Framework ◽  
Lateral Sclerosis

Neurodegenerative diseases are etiologically and clinically heterogeneous conditions, often reflecting a spectrum of disease rather than well-defined disorders. The underlying molecular complexity of these diseases has made the discovery and validation of useful biomarkers challenging. The search of characteristic genetic and transcriptomic indicators for preclinical disease diagnosis, prognosis, or subtyping is an area of ongoing effort and interest. The next generation of biomarker studies holds promise by implementing meaningful longitudinal and multi-modal approaches in large scale biobank and healthcare system scale datasets. This work will only be possible in an open science framework. This review summarizes the current state of genetic and transcriptomic biomarkers in Parkinson’s disease, Alzheimer’s disease, and amyotrophic lateral sclerosis, providing a comprehensive landscape of recent literature and future directions.

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