A Low-noise Low-offset Op Amp in 0.35μm CMOS Process

2006 ◽  
Author(s):  
Zhineng Zhu ◽  
R. Tumati ◽  
S. Collins ◽  
R. Smith ◽  
D.E. Kotecki
Keyword(s):  
Low Noise ◽  
Cmos Process ◽  
Op Amp ◽  
Low Offset

scholarly journals A Four-Channel Low-Noise Readout IC for Air Flow Measurement Using Hot Wire Anemometer in 0.18 μm CMOS Technology

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4694
Author(s):  
Kyeongsik Nam ◽  
Hyungseup Kim ◽  
Yongsu Kwon ◽  
Gyuri Choi ◽  
Taeyup Kim ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Air Flow ◽  
Low Noise ◽  
Cmos Process ◽  
Significant Information ◽  
Flow Measurements ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Op Amp ◽  
Noise Characteristics

Air flow measurements provide significant information required for understanding the characteristics of insect movement. This study proposes a four-channel low-noise readout integrated circuit (IC) in order to measure air flow (air velocity), which can be beneficial to insect biomimetic robot systems that have been studied recently. Instrumentation amplifiers (IAs) with low-noise characteristics in readout ICs are essential because the air flow of an insect’s movement, which is electrically converted using a microelectromechanical systems (MEMS) sensor, generally produces a small signal. The fundamental architecture employed in the readout IC is a three op amp IA, and it accomplishes low-noise characteristics by chopping. Moreover, the readout IC has a four-channel input structure and implements an automatic offset calibration loop (AOCL) for input offset correction. The AOCL based on the binary search logic adjusts the output offset by controlling the input voltage bias generated by the R-2R digital-to-analog converter (DAC). The electrically converted air flow signal is amplified using a three op amp IA, which is passed through a low-pass filter (LPF) for ripple rejection that is generated by chopping, and converted to a digital code by a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Furthermore, the readout IC contains a low-dropout (LDO) regulator that enables the supply voltage to drive digital circuits, and a serial peripheral interface (SPI) for digital communication. The readout IC is designed with a 0.18 μm CMOS process and the current consumption is 1.886 mA at 3.3 V supply voltage. The IC has an active area of 6.78 mm2 and input-referred noise (IRN) characteristics of 95.4 nV/√Hz at 1 Hz.

scholarly journals Active Balun with Center-Tapped Inductor and Double-Balanced Gilbert Mixer for GNSS Applications

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1351
Author(s):  
Daniel Pietron ◽  
Tomasz Borejko ◽  
Witold Adam Pleskacz
Keyword(s):  
Phase Shift ◽  
Noise Figure ◽  
Low Noise ◽  
Global Navigation Satellite Systems ◽  
Cmos Process ◽  
Differential Signal ◽  
Satellite Systems ◽  
Active Balun ◽  
Noise Amplifier ◽  
Global Navigation Satellite

A new 1.575 GHz active balun with a classic double-balanced Gilbert mixer for global navigation satellite systems is proposed herein. A simple, low-noise amplifier architecture is used with a center-tapped inductor to generate a differential signal equal in amplitude and shifted in phase by 180°. The main advantage of the proposed circuit is that the phase shift between the outputs is always equal to 180°, with an accuracy of ±5°, and the gain difference between the balun outputs does not change by more than 1.5 dB. This phase shift and gain difference between the outputs are also preserved for all process corners, as well as temperature and voltage supply variations. In the balun design, a band calibration system based on a switchable capacitor bank is proposed. The balun and mixer were designed with a 110 nm CMOS process, consuming only a 2.24 mA current from a 1.5 V supply. The measured noise figure and conversion gain of the balun and mixer were, respectively, NF = 7.7 dB and GC = 25.8 dB in the band of interest.

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process

2009 ◽  
Vol 30 (1) ◽  
pp. 015001 ◽  
Author(s):  
Yang Yi ◽  
Gao Zhuo ◽  
Yang Liqiong ◽  
Huang Lingyi ◽  
Hu Weiwu
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Noise Amplifier

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals 14.85 µW Analog Front-End for Photoplethysmography Acquisition with 142-dBΩ Gain and 64.2-pArms Noise

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 512
Author(s):  
Binghui Lin ◽  
Mohamed Atef ◽  
Guoxing Wang
Keyword(s):  
Dynamic Range ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Control Block ◽  
Silicon Area ◽  
Front End ◽  
Analog Front End

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.

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