Supply Voltage Adjustment Technique with Process-Voltage Conversion Table for Low Power Consumption

2007 ◽  
Author(s):  
Atsuki Inoue ◽  
Hiroshi Okano ◽  
Tetsuyoshi Shiota ◽  
Yukihito Kawabe ◽  
Wataru Shibamoto ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Low Power Consumption ◽  
Conversion Table ◽  
Voltage Conversion

scholarly journals The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications

2019 ◽  
Vol 3 (3) ◽  
pp. 19-27
Author(s):  
Mohsen Sadeghi ◽  
Mahya Zahedi ◽  
Maaruf Ali
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Propagation Delay ◽  
Simulation Software ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Novel Structure

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

scholarly journals CMOS Realization of Fully Electronically Tunable Single Resistance Control Mixed Mode Biquad Filter Employing Single VDTA at ± 0.6V

2021 ◽  
Vol 20 ◽  
pp. 48-57
Author(s):  
Ghanshyam Singh ◽  
Hameed Pasha ◽  
H. C. Hadimani ◽  
Zuleka Tabbusm
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Mixed Mode ◽  
Supply Voltage ◽  
Low Power Consumption ◽  
Pass Band ◽  
Power Supply Voltage ◽  
Passive Element ◽  
Biquad Filter ◽  
Filter Configuration

This paper presents a single resistance control single VDTA based Mixed Mode type Biquad filter. The proposed Transadmittance Mode (TAM) type Biquad filter configuration employed single voltage differencing transconductance amplifier (VDTA) as an active building block, three passive element namely one grounded resistor, one grounded capacitor and one floating capacitor. The proposed transadmittance Mode multifunction Biquad filter configuration is presenting transadmittance mode type four basic standard filter functions low pass, high pass, band pass, band reject or band stop or band eliminate filter responses. These four type filter responses are realizing simultaneously with the selection of single input voltage signal. The proposed Transadmittance Mode multifunction Biquad filter configuration has more advantageous features such as low active and passive sensitivities, low power supply voltage, low power consumption, low quality factor, very low power consumption, more electronic tunability, higher linearity and required small area of the chip. The performance of the proposed configuration has been verified through PSPICE simulation using 0.18μm CMOS Technology process parameters.

Analytical Study Of Full Adder Circuit Using Modified Glitch Free Cascadable Adiabatic Logic

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Neha Raghav ◽  
◽  
Malti Bansal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Analytical Study ◽  
Supply Voltage ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Adiabatic Logic

Nowadays, power dissipation is among the most dominant concerns in designing a VLSI circuits. Endless improvement in technology has points to an increased requirement for devices which have the basic characteristic of low power consumption. Hence power has turn into a demanding design parameter in low power and high-performance applications. The Adiabatic logic technique is becoming a solution to the dilemma of power dissipation. Adders with huge power consumption affect the overall efficiency of the system. Hence, in this paper, the proposed application of full adder circuit is shown using the Modified Glitch Free Cascadable Adiabatic Logic. The circuit is compared with the conventional CMOS Logic and the power dissipation analysis is simulated with supply voltage = 0.9 V, 1.2 V and 1.8 V to analyze the pattern followed with supply variation at different temperature range. Similarly, the calculation of delay is performed for temperature values of 27˚C, 55˚C and 120˚C at 90nm technology.

A 5-BIT 500-MS/S FLASH ADC USING TIME-DOMAIN COMPARISON

2012 ◽  
Vol 21 (08) ◽  
pp. 1240023 ◽  
Author(s):  
YOUNG-JAE MIN ◽  
HOON-KI KIM ◽  
CHULWOO KIM ◽  
SOO-WON KIM ◽  
GIL-SU KIM
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Time Domain ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Nyquist Frequency ◽  
Flash Adc ◽  
Digital Implementation ◽  
The Time Domain

A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 μm CMOS technology and occupies 0.132 mm2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8 mW with a 1.8-V supply voltage.

Optimal design of a high homogeneous and small-size shim coil for atomic spin gyroscope based on 0-1 linear programming

2020 ◽  
Vol 64 (1-4) ◽  
pp. 165-172
Author(s):  
Dongge Deng ◽  
Mingzhi Zhu ◽  
Qiang Shu ◽  
Baoxu Wang ◽  
Fei Yang
Keyword(s):  
Linear Programming ◽  
Power Consumption ◽  
Low Power ◽  
Optimization Design ◽  
Structural Parameters ◽  
Axial Position ◽  
Low Power Consumption ◽  
Optimal Method ◽  
Atomic Spin ◽  
Shim Coil

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power
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