scholarly journals CMOS Realization of Fully Electronically Tunable Single Resistance Control Mixed Mode Biquad Filter Employing Single VDTA at ± 0.6V

2021 ◽  
Vol 20 ◽  
pp. 48-57
Author(s):  
Ghanshyam Singh ◽  
Hameed Pasha ◽  
H. C. Hadimani ◽  
Zuleka Tabbusm
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Mixed Mode ◽  
Supply Voltage ◽  
Low Power Consumption ◽  
Pass Band ◽  
Power Supply Voltage ◽  
Passive Element ◽  
Biquad Filter ◽  
Filter Configuration

This paper presents a single resistance control single VDTA based Mixed Mode type Biquad filter. The proposed Transadmittance Mode (TAM) type Biquad filter configuration employed single voltage differencing transconductance amplifier (VDTA) as an active building block, three passive element namely one grounded resistor, one grounded capacitor and one floating capacitor. The proposed transadmittance Mode multifunction Biquad filter configuration is presenting transadmittance mode type four basic standard filter functions low pass, high pass, band pass, band reject or band stop or band eliminate filter responses. These four type filter responses are realizing simultaneously with the selection of single input voltage signal. The proposed Transadmittance Mode multifunction Biquad filter configuration has more advantageous features such as low active and passive sensitivities, low power supply voltage, low power consumption, low quality factor, very low power consumption, more electronic tunability, higher linearity and required small area of the chip. The performance of the proposed configuration has been verified through PSPICE simulation using 0.18μm CMOS Technology process parameters.

scholarly journals Implementation of Face Recognition Processing Using an Embedded Processor

2005 ◽  
Vol 17 (4) ◽  
pp. 428-436 ◽  
Author(s):  
Hiroyuki Kondo ◽  
◽  
Masami Nakajima ◽  
Miroslaw Bober ◽  
Krzysztof Kucharski ◽  
...  
Keyword(s):  
Face Recognition ◽  
Power Consumption ◽  
High Performance ◽  
Supply Voltage ◽  
Chip Multiprocessor ◽  
Low Power Consumption ◽  
Single Chip ◽  
Power Supply Voltage ◽  
Embedded Processor ◽  
Tremendous Amount

Embedded processors are conventionally difficult to use in face recognition in the security and robotic fields because of the tremendous amount of processing required. We implemented face recognition processing with a multicore based embedded processor having low power consumption and high performance. The single-chip multiprocessor is manufactured using a 0.15μm process with two M32R cores, 512KB of SRAM, and peripheral circuits integrated on a single-chip. It has a power supply voltage of 1.5V, a frequency of 600MHz, and power consumption of 800mW.

scholarly journals The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications

2019 ◽  
Vol 3 (3) ◽  
pp. 19-27
Author(s):  
Mohsen Sadeghi ◽  
Mahya Zahedi ◽  
Maaruf Ali
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Propagation Delay ◽  
Simulation Software ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Novel Structure

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

scholarly journals Miniaturised Infrared Spectrophotometer for Low Power Consumption Multi-Gas Sensing

Sensors ◽  
2020 ◽  
Vol 20 (14) ◽  
pp. 3843
Author(s):  
Manu Muhiyudin ◽  
David Hutson ◽  
Desmond Gibson ◽  
Ewan Waddell ◽  
Shigeng Song ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Gas Sensor ◽  
Gas Sensing ◽  
Optical Filters ◽  
Low Power Consumption ◽  
Practical Implementation ◽  
Pass Band ◽  
Concept Design ◽  
Infrared Source

Concept, design and practical implementation of a miniaturized spectrophotometer, utilized as a mid-infrared-based multi gas sensor is described. The sensor covers an infrared absorption wavelength range of 2.9 to 4.8 um, providing detection capabilities for carbon dioxide, carbon monoxide, nitrous oxide, sulphur dioxide, ammonia and methane. A lead selenide photo-detector array and customized MEMS-based micro-hotplate are used as the detector and broadband infrared source, respectively. The spectrophotometer optics are based on an injection moulded Schwarzschild configuration incorporating optical pass band filters for the spectral discrimination. This work explores the effects of using both fixed-line pass band and linear variable optical filters. We report the effectiveness of this low-power-consumption miniaturized spectrophotometer as a stand-alone single and multi-gas sensor, usage of a distinct reference channel during gas measurements, development of ideal optical filters and spectral control of the source and detector. Results also demonstrate the use of short-time pulsed inputs as an effective and efficient way of operating the sensor in a low-power-consumption mode. We describe performance of the spectrometer as a multi-gas sensor, optimizing individual component performances, power consumption, temperature sensitivity and gas properties using modelling and customized experimental procedures.

Analytical Study Of Full Adder Circuit Using Modified Glitch Free Cascadable Adiabatic Logic

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Neha Raghav ◽  
◽  
Malti Bansal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Analytical Study ◽  
Supply Voltage ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Adiabatic Logic

Nowadays, power dissipation is among the most dominant concerns in designing a VLSI circuits. Endless improvement in technology has points to an increased requirement for devices which have the basic characteristic of low power consumption. Hence power has turn into a demanding design parameter in low power and high-performance applications. The Adiabatic logic technique is becoming a solution to the dilemma of power dissipation. Adders with huge power consumption affect the overall efficiency of the system. Hence, in this paper, the proposed application of full adder circuit is shown using the Modified Glitch Free Cascadable Adiabatic Logic. The circuit is compared with the conventional CMOS Logic and the power dissipation analysis is simulated with supply voltage = 0.9 V, 1.2 V and 1.8 V to analyze the pattern followed with supply variation at different temperature range. Similarly, the calculation of delay is performed for temperature values of 27˚C, 55˚C and 120˚C at 90nm technology.

A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control

2018 ◽  
Vol 27 (10) ◽  
pp. 1850160 ◽  
Author(s):  
Manoj Kumar ◽  
Dileep Dwivedi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Power Supply Voltage ◽  
Back Gate ◽  
Tuning Method ◽  
Low Power Cmos ◽  
Improved Performance ◽  
Mos Varactor

This paper presents a new design of low power voltage controlled oscillator (VCO) circuit using three transistors NOR-gate and I-MOS (inversion mode) varactor tuning method. Variation in the oscillation frequency has been obtained by varying the output load capacitance with the use of I-MOS varactor tuning consisting of two PMOS transistors connected in parallel. Variable capacitance across the I-MOS varactor has been achieved by varying the source/drain voltage ([Formula: see text] and back-gate voltage ([Formula: see text]. Variation of [Formula: see text] from 1[Formula: see text]V to 2[Formula: see text]V provides the frequency deviation from 1.970[Formula: see text]GHz to 1.379[Formula: see text]GHz with I-MOS width of 8 [Formula: see text]m at power supply voltage ([Formula: see text] of 1.8[Formula: see text]V. Power consumption of the circuit is 1.296[Formula: see text]mW with [Formula: see text] of 1.8[Formula: see text]V. The results have been obtained for different I-MOS varactor widths like 5[Formula: see text][Formula: see text]m, 8[Formula: see text][Formula: see text]m and 10[Formula: see text][Formula: see text]m. Further, variations in the frequency have been obtained from 0.650 GHz to 2.584 GHz with the Vdd variation from 1[Formula: see text]V to 3[Formula: see text]V. In addition, by variations of [Formula: see text] from 0[Formula: see text]V to 1.8[Formula: see text]V and [Formula: see text] from 1[Formula: see text]V to 3[Formula: see text]V, the proposed oscillators operate in the frequency range from 0.556[Formula: see text]GHz to 2.584[Formula: see text]GHz for 8[Formula: see text][Formula: see text]m width of I-MOS varactor. Proposed VCO circuit show a phase noise of [Formula: see text][Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset from the carrier frequency and the figure of merit (FoM) for the VCO is 154.51[Formula: see text]dB/Hz. Proposed VCO shows an improved performance in terms of power consumption, output frequency and FoM.

A 5-BIT 500-MS/S FLASH ADC USING TIME-DOMAIN COMPARISON

2012 ◽  
Vol 21 (08) ◽  
pp. 1240023 ◽  
Author(s):  
YOUNG-JAE MIN ◽  
HOON-KI KIM ◽  
CHULWOO KIM ◽  
SOO-WON KIM ◽  
GIL-SU KIM
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Time Domain ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Nyquist Frequency ◽  
Flash Adc ◽  
Digital Implementation ◽  
The Time Domain

A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 μm CMOS technology and occupies 0.132 mm2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8 mW with a 1.8-V supply voltage.

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