Application of Broadband RF Metrology to Integrated Circuit Interconnect Reliability Analyses: Monitoring Copper Interconnect Corrosion in 3D-ICs

Author(s):  
Papa K. Amoah ◽  
Jesus Perez ◽  
Yaw S. Obeng
Author(s):  
Qiang Gao ◽  
Mark Zhang ◽  
Ming Li ◽  
Chorng Niou ◽  
W.T. Kary Chien

Abstract This paper examines copper-interconnect integrated circuit transmission electron microscope (TEM) sample contamination. It investigates the deterioration of the sample during ion milling and storage and introduces prevention techniques. The paper discusses copper grain agglomeration issues barrier/seed step coverage checking. The high temperature needed for epoxy solidifying was found to be harmful to sidewall coverage checking of seed. Single beam modulation using a glass dummy can efficiently prevent contamination of the area of interest in a TEM sample during ion milling. Adoption of special low-temperature cure epoxy resin can greatly reduce thermal exposure of the sample and prevent severe agglomeration of copper seed on via sidewall. TEM samples containing copper will deteriorate when stored in ordinary driers and sulphur contamination was found at the deteriorated point on the sample. Isolation of the sample from the ambient atmosphere has been verified to be very effective in protecting the TEM sample from deterioration.


Author(s):  
Jackson B. Marcinichen ◽  
John R. Thome

For the next generation of high performance computers, the new challenges are to shorten the distance for transporting data (to accelerate the transfer of information) between multi-microprocessors and memories, and to cool these electronic components despite the increased heat flux that results from increased transistor density. Recent technological advances show a tendency for the development of 3D integrated circuit stacked architectures with interlayer cooling (multi-microchannels in the silicon layers). However, huge challenges exist in such design/concept, i.e. flow distribution to hundreds microchannels distributed in the different interlayers, thermo-hydrodynamic and geometrical limitations, manufacturing etc. 3D-ICs with interlayer cooling are still about a decade away, so a viable shorter term goal is 3D stacks with backside cooling, taking advantage of Si layers now able to be thineer down to only 50 μm thickness. Thus, the present work presents thermo-hydrodynamic simulations for 3D stacks considering only a backside cooler, which simplifies considerably the assembly and guarantees a high level of reliability. In summary, the results showed that this concept is thermally feasible and potentially that interlayer microchannels (between stacks) will not be necessary.


1993 ◽  
Vol 309 ◽  
Author(s):  
Jamie H. Rose ◽  
Terry Spooner

AbstractIt is well known that stress and electromigration induced voiding is of major concern for integrated circuit interconnect reliability. However, there has been little systematiccharacterization of void morphology and crystallography in ever more technologically important narrow, “near-bamboo” conducting lines. Prior reports indicate thatvoids are typically wedge or slit shaped, with failure often associated with slit voids.Void face habit plane is most often reported to be {111}. Wedge and slit void morphology and crystallography have been studied in comb/serpentine and parallel line array test structures. In virtually all cases, void faces are {111} oriented. In contrast to earlier studies, intragranular wedge stress voids have been observed. All electromigration opens were due to slit voids; these were typically intragranular, in contradiction to current theories of void formation, and likely are mechanical fractures. Under accelerated test conditions, non-grain boundary diffusion paths appear to operate at distances of tens of micrometers. Relative displacement between wedge voids and attached grain boundaries occurs where a wedge face lies on a near common {111} plane for the two grains. It is suggested that slit voids are intragranular under both stress and electromigration conditions and likely associated with local interconnect depassivation. Based solely on appearance and crystallography, no void can uniquely be identified as due to stress alone or electromigration alone.


1994 ◽  
Vol 337 ◽  
Author(s):  
A.G. Dirks ◽  
R.A. Augur ◽  
S. Kordić ◽  
R.A.M. Wolters

ABSTRACTDifficulty during plasma etching and post-etch corrosion are major drawbacks of Al-Si-Cu alloy films, when used for integrated circuit interconnect. Moreover, the relatively large solute mobility of Cu in Al may lead to void formation by precipitate coarsening. As integrated circuit dimensions decrease reliability issues, such as electromigration and mechanical stress voiding, are becoming increasingly important. At present several types of Al alloys are considered as possible alternatives for Al-Si-Cu: Al-Pd, Al-Sc, Al-Pd-Cu, Al-Si-Pd, Al-Si-V, Al-Si-Sc, Al-Si-Pd-Nb, and Al-Si-V-Pd. The latter quaternary alloy has been designed such as to combine the positive aspects of both Pd and V. In comparison with Cu in Al, a) the (low temperature) solid solubility is negligible for Pd and small for V, and b) the mobility is similar for Pd, but very small for V.With transmission-electron microscopy, passivated Al-Si-Cu alloy films have been studied after thermal stressing at 200 °C: ө-Al2Cu coarsening was observed together with void condensation. Lifetests on unpassivated Al-Si-V-Pd alloys at 180 °C and 2xl06A/cm2 have shown an extremely high resistance to electromigration. Electromigration and microstructural data on these quaternary alloys will be presented. These findings suggest how the microstructure is stabilized by the combined action of the V and Pd solute atoms, a) by nm-scale (A1,V) precipitates within the Al grains and b) by small (Al,Pd) particles at the Al grain boundaries. Furthermore, the key issues in terms of reliability related microstructural phenomena are both solute and solvent mobilities in grain interiors as well as along interfaces and grain boundaries. Arguments will be given showing that at low solute concentrations the metals (V and Pd) each by themselves are not effective enough to influence the solvent motion of aluminium along interfaces and grain boundaries significantly. The combination of the two metals, however, was found to be very effective.


2019 ◽  
Vol 34 (1) ◽  
pp. 775-780
Author(s):  
Xiao-Wen Hu ◽  
Paulchang Lin ◽  
Jenny Ma ◽  
Jian-Yong Jiang ◽  
Peng He

2003 ◽  
Vol 766 ◽  
Author(s):  
Y. Kwon ◽  
A. Jinda ◽  
J.J. McMahon ◽  
J.Q. Lu ◽  
R.J. Gutmann ◽  
...  

AbstractA process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.


2020 ◽  
Vol 12 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Kui-Zhi Wang

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic


Sign in / Sign up

Export Citation Format

Share Document