A study of signal integrity issues in through-silicon-via-based 3D ICs

2010 ◽  
Author(s):  
Chang Liu ◽  
Sung Kyu Lim
Keyword(s):  
Signal Integrity ◽  
Through Silicon Via ◽  
3D Ics

Structural Optimization of Ground Vias for 3D ICs

2011 ◽  
Vol 189-193 ◽  
pp. 1472-1475
Author(s):  
Chun Quan Li ◽  
Xiao Le Kuang
Keyword(s):  
Signal Integrity ◽  
Structure Parameters ◽  
Regression Equations ◽  
Transmission Performance ◽  
Range Analysis ◽  
3D Ics ◽  
Ic Manufacturing ◽  
Optimization Parameter ◽  
Microelectronics Industry ◽  
The Impact

Nowadays, IC manufacturing meet the challenges of physical limits, through silicon via(TSV) technology has increasingly become the focus of the microelectronics industry due to its shorter wiring route, better signal integrity, larger bandwidth, lower power consumption and smaller packaging size. In this paper, the transmission performance of TSV was analyzed and the impact of ground vias number, diameter and pitch with TSV on TSV transmission performance. A design of experiment (DOE) was established to investigate the impact of different ground vias parameter combinations on the transmission of TSV and the range analysis of the experiment results was executed. Based on the DOE, two regression equations were formed to estimate the electrical performances of TSV. From the two equations, the structure parameters were optimized, the S11 and S21 results of optimization parameter combination reduced 0.4dB and 0.15dB, respectively.

Signal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM)

2021 ◽  
Author(s):  
Seongguk Kim ◽  
Taein Shin ◽  
Hyunwook Park ◽  
Daehwan Lho ◽  
Keeyoung Son ◽  
...  
Keyword(s):  
Signal Integrity ◽  
Through Silicon Via ◽  
High Bandwidth

Understanding size effects in the advanced through-silicon via interconnect schemes for 3D ICs

2016 ◽  
Author(s):  
Imran Ali ◽  
Ihor Radchenko ◽  
Sasi Kumar Tippabhotla ◽  
Song Wenjian M. Ridhuan ◽  
Andrew A. O. Tay ◽  
...  
Keyword(s):  
Size Effects ◽  
Through Silicon Via ◽  
3D Ics

Propagation Delay Analysis in 3D Stacked Memory using Novel MOS Depletion Layer Modeling Approach for Through Silicon Via

2012 ◽  
Vol 2012 (1) ◽  
pp. 000318-000325
Author(s):  
Kaushal Kannan ◽  
Sarma G. Harihara ◽  
Sukeshwar Kannan
Keyword(s):  
Random Access ◽  
Propagation Delay ◽  
Array Size ◽  
Key Factors ◽  
Through Silicon Via ◽  
Modeling And Analysis ◽  
Memory Array ◽  
3D Ics ◽  
Doping Profiles ◽  
Stacked Memory

This paper presents the physical level design analysis of 3D stacked memory ICs with Through Silicon Via (TSV) to compute the propagation delay. The difficulties in incorporating TSVs for 3D ICs are that TSV has additional complex parasitics, process based variations, and structure based reliability issues, thus warranting detailed modeling and analysis. TSVs are known to have a MOS structure which has been rigorously studied to evaluate the overall TSV performance and the effect of variable wafer doping profiles has been included in our analysis. Our proposed TSV model provides the IC designer with the yardstick for optimum TSV pitch. Furthermore, our model considers the TSVs to have a variable capacitor which enables frequency selective characteristics based on signal strength and operating frequency. Finally, we have incorporated our model towards optimization of memory array size in 3D stacked DRAMs while taking into account the key factors of TSV delay for a given process node and TSV pitch. This exhaustive analysis would help to choose optimum memory array size while stacking, without degradation in overall 3D Dynamic Random Access Memory (DRAM) performance, and can be effectively used as a primary guideline during memory stacking and layout for optimum bandwidth.

Thermal effects on through-silicon via (TSV) signal integrity

2012 ◽  
Author(s):  
Manho Lee ◽  
Jonghyun Cho ◽  
Joohee Kim ◽  
Jun So Pak ◽  
Hyungdong Lee ◽  
...  
Keyword(s):  
Thermal Effects ◽  
Signal Integrity ◽  
Through Silicon Via
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