Signal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM)

2021 ◽  
Author(s):  
Seongguk Kim ◽  
Taein Shin ◽  
Hyunwook Park ◽  
Daehwan Lho ◽  
Keeyoung Son ◽  
...  
Keyword(s):  
Signal Integrity ◽  
Through Silicon Via ◽  
High Bandwidth

scholarly journals Design of 2.5D Interposer in High Bandwidth Memory and Through Silicon Via for High Speed Signal

2020 ◽  
Author(s):  
Bo Pu
Keyword(s):  
Artificial Intelligence ◽  
High Speed ◽  
High Performance ◽  
Equivalent Model ◽  
Electrical Characteristics ◽  
Through Silicon Via ◽  
High Bandwidth ◽  
Signal Path ◽  
High Speed Switching ◽  
Performance Computing

<p>The 2.5D interposer becomes a crucial solution to realize grand bandwidth of HBM for the increasing data requirement of high performance computing (HPC) and Artificial Intelligence (AI) applications. To overcome high speed switching bottleneck caused by the large resistive and capacitive characteristics of interposer, design methods to achieve an optimized performance in a limited routing area are proposed. Unlike the conventional single through silicon via (TSV), considering the reliability, multiple TSV are used as the robust 3D interconnects for each signal path. An equivalent model to accurately describe the electrical characteristics of the multiple TSVs, and a configuration pattern strategy of TSV to mitigate crosstalk are also proposed.</p>

Analysis on Signal and Power Integrity of 2.3D Structure Organic Package

2019 ◽  
Vol 2019 (1) ◽  
pp. 000381-000386 ◽  
Author(s):  
Kosuke Tsukamoto ◽  
Atsunori Kajiki ◽  
Yuji Kunimoto ◽  
Masayuki Mizuno ◽  
Manabu Nakamura ◽  
...  
Keyword(s):  
Power Distribution ◽  
Signal Integrity ◽  
High Density ◽  
Point Of View ◽  
Power Delivery ◽  
Power Integrity ◽  
Power Distribution Network ◽  
Organic Packages ◽  
High Bandwidth ◽  
Vertical Interconnection

Abstract Heterogeneous packaging is one of the advanced technologies. Especially for high-end applications such as data center server, HPC and Artificial-Intelligence (AI), High-Bandwidth Memory (HBM) integration is a key and strongly required. As we know, the 2.5D silicon interposer packaging is an expanded solution for HBM interconnections. However, we developed 2.1D high density organic package called i-THOP® (integrated-Thin film High density Organic Package) to take advantages of an organic solution. Furthermore, we are now focusing on 2.3D i-THOP® to have more benefits in the manufacturing. The 2.3D structure consists of two substrates. One is a thin i-THOP® interposer, the other one is a conventional build-up (BU) substrate. These two substrates are combined as the interposer placed onto the build-up substrate. In this paper, the electrical properties of 2.3D i-THOP® are studied to confirm the possibility of the 2.3D structure organic packages from the perspective of signal and power integrity. Firstly, the signal integrity between two devices is simulated, comparing the differences between i-THOP® and the 2.5D silicon interposer. Secondly, the signal integrity in die-to-substrate vertical interconnection is simulated, comparing between 2.1D, 2.3D i-THOP® and the 2.5D silicon interposer. Finally, as for the power delivery point of view, power distribution network (PDN) impedance is compared between 2.1D and 2.3D i-THOP®.

Quality and Reliability of 3D High-Performance Heterogeneous Integration through Die Stacking

2012 ◽  
Vol 2012 (1) ◽  
pp. 000249-000253 ◽  
Author(s):  
Bahareh Banijamali ◽  
Liam Madden ◽  
Suresh Ramalingam ◽  
Ephrem Wu
Keyword(s):  
High Performance ◽  
Signal Integrity ◽  
3D Integration ◽  
Die Stacking ◽  
High Bandwidth ◽  
Low K ◽  
Optimal Signal ◽  
Very High ◽  
Package Reliability ◽  
Underfill Material

This paper studies package reliability for the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration) delivering up to 2.78 Tb/s transceiver bandwidth. Each device is packaged on a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. 3D thermal-mechanical simulations are built to analyze package warpage, low-k stresses, microbumps and C4 bumps fatigue as well as BGA ball reliability. Different substrate sizes and designs, lid designs, lid materials and C4 bump underfill materials are investigated in order to optimize package reliability. LTCC ceramic package reduces fatigue in C4 bumps when increasing the risk for BGA balls to fail in thermal stressing. Hence, lid design and C4 bump underfill material are optimized to increase fatigue life for BGA balls. Simulation results indicate heterogeneous stacked-silicon (3D) integration is a reliable method to build very high-bandwidth multi-chip devices that exceed current monolithic capabilities.

Thermal effects on through-silicon via (TSV) signal integrity

2012 ◽  
Author(s):  
Manho Lee ◽  
Jonghyun Cho ◽  
Joohee Kim ◽  
Jun So Pak ◽  
Hyungdong Lee ◽  
...  
Keyword(s):  
Thermal Effects ◽  
Signal Integrity ◽  
Through Silicon Via
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