scholarly journals An 11 Bit Sub-Ranging SAR ADC with Input Signal Range of Twice Supply Voltage

2007 ◽  
Author(s):  
Devrim Aksin ◽  
Mohammad A. Al-Shyoukh ◽  
Franco Maloberti
Keyword(s):  
Input Signal ◽  
Supply Voltage ◽  
Sar Adc

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

A 12-Bit 31.1-$\mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance

2019 ◽  
Vol 54 (4) ◽  
pp. 937-947 ◽  
Author(s):  
Junhua Shen ◽  
Akira Shikata ◽  
Anping Liu ◽  
Baozhen Chen ◽  
Frederick Chalifoux
Keyword(s):  
Input Signal ◽  
Sar Adc ◽  
On Chip ◽  
Independent Calibration

scholarly journals The use of the localization method for calculation of the robust PID regulator parameters for unmanned aircraft servo motor

2020 ◽  
Vol 23 (1) ◽  
pp. 95-105
Author(s):  
A. A. Sanko ◽  
A. A. Sheinikov ◽  
T. A. Tishchenko ◽  
D. A. Smolskiy
Keyword(s):  
Input Signal ◽  
Pid Controller ◽  
Supply Voltage ◽  
Unmanned Aircraft ◽  
Discrete Control ◽  
Continuous Systems ◽  
Servo Motor ◽  
Servo Drive ◽  
Localization Method ◽  
Control Circuits

The problem of controlling a typical nonlinear servo motor of an unmanned aercraft with non-stationary parameters using a robust PID controller is considered. The procedure for calculating the parameters of a robust PID controller based on the localization method (further - LM PID controller) for continuous and discrete control systems is studied. The influence of disturbing factors (internal and external) acting on the servo motor is considered. It is established that the main perturbations acting on the servo drive include internal perturbations, which are changes in the time constant and its gain from the temperature of the environment and the quality of the supply voltage. The simulation in the class of linear and nonlinear continuous systems showed that a servo drive with a ML PID controller has the property of robustness in the working range of changes in both the input signal and the parameters of the servo drive and controller. Simulation results showing the research are presented. When describing a servo motor with an LM PID controller in the class of linear discrete systems, its robustness is limited by a narrow range of variation of both its parameters and the quantization period of the input signal. As the degree of uncertainty in the parameters of the servo motor increases (approaching the working range of their change), the discrete system loses stability. For the synthesis of robust control circuits of an unmanned aercraft with given characteristics, mathematical dependences of the settling time and static error of a typical servo motor with LM PID controller from the quantization period of the input signal and the degree of uncertainty in its parameters are presented.

A Low-Power, Signal-Specific SAR ADC for Neural Sensing Applications

2018 ◽  
Vol 27 (14) ◽  
pp. 1850230 ◽  
Author(s):  
Samaneh Babayan-Mashhadi ◽  
Mona Jahangiri-Khah
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Power Saving ◽  
Cmos Technology ◽  
Sar Adc ◽  
Signal Acquisition ◽  
Quantization Scheme ◽  
Power Efficient ◽  
Sensing Applications

As power consumption is one of the major issues in biomedical implantable devices, in this paper, a novel quantization method is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) which can save 80% power consumption in contrast to conventional structure for electroencephalogram (EEG) signal recording systems. According to the characteristics of neural signals, the principle of the proposed power saving technique was inspired such that only the difference between current input sample and the previous one is quantized, using a power efficient SAR ADC with fewer resolutions. To verify the proposed quantization scheme, the ADC is systematically modeled in Matlab and designed and simulated in circuit level using 0.18[Formula: see text][Formula: see text]m CMOS technology. When applied to neural signal acquisition, spice simulations show that at sampling rate of 25[Formula: see text]kS/s, the proposed 8-bit ADC consumes 260[Formula: see text]nW of power from 1.8[Formula: see text]V supply voltage while achieving 7.1 effective number of bits.

A Simple and Efficient Charge Injection Error Compensation Structure for MOS Sampling Switches

2018 ◽  
Vol 27 (08) ◽  
pp. 1850130 ◽  
Author(s):  
Saeed Naghavi ◽  
Mojde Nematzade ◽  
Niloofar Sharifi ◽  
Tohid Moradi Khanshan ◽  
Adib Abrishamifar ◽  
...  
Keyword(s):  
Input Signal ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Charge Injection ◽  
Sampled Data ◽  
Sampling Errors ◽  
Wide Range ◽  
Sinusoidal Input ◽  
Simulation Results

This paper introduces a new technique to design an analog MOS switch to be used in sampled-data circuits. In any sampled-data system, the accuracy of the sampling switch is a critical parameter to determine the overall performance of the system. To satisfy accuracy requirements of the switch, a novel technique to reduce channel charge injection error is proposed. The proposed switch has a very simple structure and it uses a small area of the chip. Also, it has a low on-resistance and its variation over the input signal range is acceptable. In order to evaluate the performance of the proposed switch, simulations are done in a 0.18[Formula: see text][Formula: see text]m standard CMOS technology. Simulation results show that the sampling errors produced by the channel charge injection is eliminated through a cancellation technique using an auxiliary transistor. The output error charge due to charge injection over a wide range of the input signal variation is very low (less than 1.45[Formula: see text]fC). Also, simulation results show that the proposed switch achieves signal-to-noise plus distortion ratio (SNDR) of 85.05[Formula: see text]dB, effective number of bits (ENOB) of 13.83, total harmonic distortion (THD) of [Formula: see text]87.23[Formula: see text]dB and spurious-free dynamic range (SFDR) of 88.14[Formula: see text]dB for a 1[Formula: see text]MHz sinusoidal input of 800[Formula: see text]mV peak-to-peak amplitude at 50[Formula: see text]MHz sampling rate with a 1.8[Formula: see text]V supply voltage.

A low power mixed signal correlator for power efficient sound signature detection and template matching

Sensor Review ◽  
2017 ◽  
Vol 37 (3) ◽  
pp. 213-222 ◽  
Author(s):  
Mehdi Habibi ◽  
Mohammad Shakarami ◽  
Ali Asghar Khoddami
Keyword(s):  
Low Power ◽  
Input Signal ◽  
Template Matching ◽  
Supply Voltage ◽  
Energy Resource ◽  
Low Power Design ◽  
Sound Signal ◽  
Mixed Signal ◽  
Content Type ◽  
Signature Detection

Purpose Sensor networks have found wide applications in the monitoring of environmental events such as temperature, earthquakes, fire and pollution. A major challenge with sensor network hardware is their limited available energy resource, which makes the low power design of these sensors important. This paper aims to present a low power sensor which can detect sound waveform signatures. Design/methodology/approach A novel mixed signal hardware is presented to correlate the received sound signal with a specific sound signal template. The architecture uses pulse width modulation and a single bit digital delay line to propagate the input signal over time and analog current multiplier units to perform template matching with low power usage. Findings The proposed method is evaluated for a chainsaw signature detection application in forest environments, under different supply voltage values, input signal quantization levels and also different template sample points. It is observed that an appropriate combination of these parameters can optimize the power and accuracy of the presented method. Originality/value The proposed mixed signal architecture allows voltage and power reduction compared with conventional methods. A network of these sensors can be used to detect sound signatures in energy limited environments. Such applications can be found in the detection of chainsaw and gunshot sounds in forests to prevent illegal logging and hunting activities.

scholarly journals A low-power 10-bit 6.66 MS/s CMOS SAR ADC with built-in digital calibration dedicated to Wireless Sensor Networks applications

2018 ◽  
Vol 13 (3) ◽  
pp. 1-8
Author(s):  
Felipe Makara ◽  
Lucas Mangini da Silva ◽  
Luis Henrique Assumpção Lolis ◽  
Andre Mariano
Keyword(s):  
Wireless Sensor Networks ◽  
Input Signal ◽  
Energy Efficient ◽  
Sar Adc ◽  
Digital Calibration ◽  
Wireless Sensor ◽  
Trade Off ◽  
Iot Applications ◽  
Improve Accuracy ◽  
Binary Weighted

In this paper, an energy-efficient SAR ADC for IoT applications is presented. The proposed ADC relies on a built-in calibration circuit to improve accuracy and introduces an original DAC that merges the concepts of binary-weighted and C/2C arrays in order to achieve a favorable trade-off between area, accuracy and power consumption. The system consumes 58 µW per conversion cycle sampling at a frequency of 6.66 MHz with an SNDR of 49.78 dB for a 1MHz input signal. With an ENOB of 8 bits, the resulting FOM is 34fJ/conversion-step.

A 9-bit 10MSps SAR ADC with double input range for supply voltage

2017 ◽  
Author(s):  
Gong Chen ◽  
Weiwei Ling ◽  
Rui Yang ◽  
Li Li ◽  
Hua Wei ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Sar Adc ◽  
Input Range
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