Prolog to: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits

2003 ◽  
Vol 91 (2) ◽  
pp. 303-304 ◽  
Author(s):  
H. Falk
Keyword(s):  
Leakage Current ◽  
Cmos Circuits ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Deep Submicrometer

scholarly journals LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY

2013 ◽  
pp. 237-242
Author(s):  
B. DILIP ◽  
P. SURYA PRASAD ◽  
R. S. G. BHAVANI
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Power Reduction ◽  
The Other ◽  
Cmos Circuits ◽  
Reduction Techniques ◽  
Additional Control ◽  
Area Increase ◽  
Leakage Control ◽  
Additional Resistance

In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the additional resistance thereby reducing the leakage current in the path. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along with this, the other advantage with LECTOR technique is that it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques.

scholarly journals Modified LECTOR Technique for Level Shifters

2019 ◽  
Vol 8 (11) ◽  
pp. 1705-1708
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Logic Gate ◽  
The Other ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Leakage Control ◽  
Static Power ◽  
Level Shifter ◽  
P Type

Static power dissipation is a major problem in CMOS circuits and this is due to the increase in sub threshold leakage current which is the effect of voltage scaling and also leading to reducing the threshold voltage. Here we propose Lector technique to reduce the leakage current and at the same time it will not increase the dynamic power dissipation. Two leakage control transistors of which one is p-type and the other one is n-type were introduced into the logic gate. The source of one transistor controls the gate terminal of the other transistor. For any combination of input one of the two leakage control transistors will be near to its cutoff voltage by this the leakage currents can be minimized as the path resistance to ground will increase. For both idle and active states of circuit the proposed Lector technique is applicable which will result in more leakage reduction when compared to remaining techniques used for leakage reduction and it will also out pass the limitations Occurred due to the implementation of other power and delay reduction techniques. Experimental results indicate a delay is reduced by 50.3% and power is reduced by 94.4% for proposed level shifter circuits.

LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES

2011 ◽  
Vol 20 (01) ◽  
pp. 147-162 ◽  
Author(s):  
WEIQIANG ZHANG ◽  
LI SU ◽  
YU ZHANG ◽  
LINFENG LI ◽  
JIANPING HU
Keyword(s):  
Total Power ◽  
High Threshold ◽  
Leakage Currents ◽  
Flip Flop ◽  
Leakage Reduction ◽  
Low Leakage ◽  
Reduction Techniques ◽  
Low Threshold ◽  
Critical Paths ◽  
P Type

The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

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