scholarly journals Modified LECTOR Technique for Level Shifters

2019 ◽  
Vol 8 (11) ◽  
pp. 1705-1708
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Logic Gate ◽  
The Other ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Leakage Control ◽  
Static Power ◽  
Level Shifter ◽  
P Type

Static power dissipation is a major problem in CMOS circuits and this is due to the increase in sub threshold leakage current which is the effect of voltage scaling and also leading to reducing the threshold voltage. Here we propose Lector technique to reduce the leakage current and at the same time it will not increase the dynamic power dissipation. Two leakage control transistors of which one is p-type and the other one is n-type were introduced into the logic gate. The source of one transistor controls the gate terminal of the other transistor. For any combination of input one of the two leakage control transistors will be near to its cutoff voltage by this the leakage currents can be minimized as the path resistance to ground will increase. For both idle and active states of circuit the proposed Lector technique is applicable which will result in more leakage reduction when compared to remaining techniques used for leakage reduction and it will also out pass the limitations Occurred due to the implementation of other power and delay reduction techniques. Experimental results indicate a delay is reduced by 50.3% and power is reduced by 94.4% for proposed level shifter circuits.

scholarly journals LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY

2013 ◽  
pp. 237-242
Author(s):  
B. DILIP ◽  
P. SURYA PRASAD ◽  
R. S. G. BHAVANI
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Power Reduction ◽  
The Other ◽  
Cmos Circuits ◽  
Reduction Techniques ◽  
Additional Control ◽  
Area Increase ◽  
Leakage Control ◽  
Additional Resistance

In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the additional resistance thereby reducing the leakage current in the path. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along with this, the other advantage with LECTOR technique is that it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques.

LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES

2011 ◽  
Vol 20 (01) ◽  
pp. 147-162 ◽  
Author(s):  
WEIQIANG ZHANG ◽  
LI SU ◽  
YU ZHANG ◽  
LINFENG LI ◽  
JIANPING HU
Keyword(s):  
Total Power ◽  
High Threshold ◽  
Leakage Currents ◽  
Flip Flop ◽  
Leakage Reduction ◽  
Low Leakage ◽  
Reduction Techniques ◽  
Low Threshold ◽  
Critical Paths ◽  
P Type

The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

TECHNIQUES FOR LOW LEAKAGE NANOSCALE VLSI CIRCUITS: A COMPARATIVE STUDY

2014 ◽  
Vol 23 (05) ◽  
pp. 1450061 ◽  
Author(s):  
VIJAY KUMAR SHARMA ◽  
MANISHA PATTANAIK
Keyword(s):  
Threshold Voltage ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Deep Submicron ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Leakage Power Dissipation

Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-off the performance yield and leakage power dissipation in nanoscaled devices. Low threshold voltage improves the device characteristics with large leakage power in nanoscaled devices. Several leakage reduction techniques at different levels are used to mitigate the leakage power dissipation. Lower leakage power increases the reliability by reducing the cooling cost of the portable systems. In this article, we are presenting the explanatory general review of the commonly used leakage reduction techniques at circuit level. We have analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at different technology nodes in active as well as standby modes. Process, voltage and temperature effects are checked for reliability purpose. Our comparative results and discussion of different leakage reduction techniques are very useful to illustrate the effective technique in active and standby modes.

Leakage Reduction Techniques of P-type Adiabatic Circuits Based on Dual-threshold and Gate-length Biasing

2013 ◽  
Vol 12 (22) ◽  
pp. 6513-6518
Author(s):  
Cheng Wei ◽  
Zhang Xia ◽  
Hu Jian-Ping ◽  
Han Cheng-Hao
Keyword(s):  
Gate Length ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
P Type

scholarly journals Design of Self Controllable Voltage Level Circuit (SVL) for Low Power and High Speed 12t Sram at 15nm Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 1561-1565
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
High Speed ◽  
Average Power ◽  
Dissipation Factor ◽  
Main Concern ◽  
Main Task ◽  
Voltage Level ◽  
Reduction Techniques

Due to trend of decreasing the device Size and increase in the chip density, the complexity in design increased and it became very complex. The main factor which is main concern in this step is Power dissipation. This can be occurring in many forms like Dynamic, subthreshold leakage and Gate leakage. For every situation the designer has to try to reduce this Power Dissipation factor. In this paper we designed a low power 12T SRAM by using the 15nm technology. SRAMs have large number of applications in high speed registers, microprocessors, small memory banks, general computing applications etc. Therefore delay, power, speed, leakage current and stability are the main concerns. These parameters are in trade off to each other. This paper focuses on the leakage current, power and stability in 12T SRAM bit -cell. We introduce a circuit “self - controllable Voltage Level (SVL)” circuit. The main task of this circuit is to reduce the stand-by leakage power of 12T SRAM. In our Work, We are using the Cadence Virtuoso simulation tool for simulating our circuit. After Comparing our results to the previous methods used for reducing the power leakage we found that there is reduction in average power compare to the previous methods used for power reduction techniques.

Influence of Overgrown Micropipes in the Active Area of SiC Schottky Diodes on Long Term Reliability

2005 ◽  
Vol 483-485 ◽  
pp. 925-928 ◽  
Author(s):  
Roland Rupp ◽  
Michael Treu ◽  
Peter Türkes ◽  
H. Beermann ◽  
Thomas Scherg ◽  
...  
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Schottky Diodes ◽  
Physical Structure ◽  
Active Area ◽  
Clear Correlation ◽  
Local Power ◽  
Degradation Mechanisms ◽  
Failure Simulation

Other than open micropipes (MP), overgrown micropipes do not necessarily lead to a^significantly reduced blocking capability of the affected SiC device. However they can lead to a degradation of the device during operation. In this paper the physical structure of overgrown micropipes will be revealed and their contribution to the leakage current will be shown. The possible impact of the high local power dissipation in the surrounding of the overgrown micropipe will be discussed and long term degradation mechanisms will be described. Failure simulation under laboratory conditions shows a clear correlation between the position of overgrown micropipes and the location of destructive burnt spots.

Study on Schottky Diode Characteristics Improving by X-Ray Irradiation

2013 ◽  
Vol 717 ◽  
pp. 113-116
Author(s):  
Sani Klinsanit ◽  
Itsara Srithanachai ◽  
Surada Ueamanapong ◽  
Sunya Khunkhao ◽  
Budsara Nararug ◽  
...  
Keyword(s):  
Leakage Current ◽  
Schottky Diode ◽  
Room Temperature ◽  
The Other ◽  
Low Power Consumption ◽  
Initial Value ◽  
X Ray ◽  
Forward Current ◽  
Current Voltage ◽  
Current Voltage Characteristics

The effect of soft X-ray irradiation to the Schottky diode properties was analyzed in this paper. The built-in voltage, leakage current, and work function of Schottky diode were investigated. The current-voltage characteristics of the Schottky diode are measured at room temperature. After irradiation at 70 keV for 55 seconds the forward current and leakage current are increase slightly. On the other hand, the built-in voltage is decrease from the initial value about 0.12 V. Consequently, this method can cause the Schottky diode has low power consumption. The results show that soft X-ray can improve the characteristics of Schottky diode.

scholarly journals ZTC bias point of advanced fin based device: The importance and exploration

2015 ◽  
Vol 28 (3) ◽  
pp. 393-405 ◽  
Author(s):  
Sushanta Mohapatra ◽  
Kumar Pradhan ◽  
Prasanna Sahu
Keyword(s):  
Power Dissipation ◽  
Temperature Compensation ◽  
Performance Metrics ◽  
Zero Temperature ◽  
Sweet Spot ◽  
Static Power ◽  
20 Nm ◽  
Bias Point ◽  
The Impact ◽  
Present Understanding

The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25?C to 225?C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static power dissipation (PD), energy (E), energy delay product (EDP), and sweet spot (gmfT/ID) of the FinFET is successfully carried out by commercially available TCAD simulator SentaurusTM from Synopsis Inc.

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