Voltage reference design using 1 V power supply in 0.13 µm CMOS technology

2013 ◽  
Author(s):  
D. Colombo ◽  
G. Wirth ◽  
S. Bampi ◽  
P. Srinivasan
Keyword(s):  
Power Supply ◽  
Cmos Technology ◽  
Voltage Reference ◽  
Reference Design

A High-Order Curvature-Compensated Bandgap Voltage Reference for Micro-Gyroscope

2012 ◽  
Vol 503 ◽  
pp. 12-17
Author(s):  
Qiang Li ◽  
Xiao Yun Tan ◽  
Guan Shi Wang
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Bandgap Reference ◽  
Voltage Reference ◽  
Temperature Dependent ◽  
Power Supply Voltage ◽  
Gyroscope System ◽  
Bandgap Voltage Reference ◽  
Reference Circuit

The reference is an important part of the micro-gyroscope system. The precision and stability of the reference directly affect the precision of the micro-gyroscope. Unlike the traditional bandgap reference circuit, a circuit using a temperature-dependent resistor ratio generated by a highly-resistive poly resistor and a diffusion resistor in CMOS technology is proposed in this paper. The complexity of the circuit is greatly reduced. Implemented with the standard 0.5μm CMOS technology and 9V power supply voltage, in the range of -40~120°C, the temperature coefficient of the proposed bandgap voltage reference can achieve to about 1.6 ppm/°C. The PSRR of the circuit is -107dB.

Thermally Reliable Ultra-Low-Power Voltage Reference to Regulator Converter

2020 ◽  
pp. 2150024
Author(s):  
George M. Joseph ◽  
Emmanouel George ◽  
Prathyush S. Pramod ◽  
Zameel Nizam ◽  
S. Krishnapriya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Current Efficiency ◽  
Power Supply ◽  
Cmos Technology ◽  
Surveillance Systems ◽  
Voltage Reference ◽  
Power Budget ◽  
Line Load ◽  
Ultra Low Power

A regulated power supply with ultra-low-power consumption, high current efficiency, line, load and thermal stability is an essential part of any high precision electronic system with stringent power budget such as biomedical sensors or military surveillance systems. In this paper, we propose an ultra-low-power, MOSFET only, voltage reference to regulator convertor, proficient to work below 1 V with reduced power consumption. The proposed idea incorporates the provision to integrate any voltage reference module to a comparator-based circuit so as to transform it to a voltage regulator having similar temperature coefficient (TC) and line regulation as that of the interfaced voltage reference. It is also able to produce a reliable output accounting to load fluctuations. The circuit is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology using Cadence Virtuoso simulation suit. The complete circuit was found to draw a quiescent current of 319.9 pA with a notable current efficiency of 99.99997% at 27∘C on driving a load of 1[Formula: see text]mA along with a Power Supply Rejection Ratio (PSRR) of [Formula: see text][Formula: see text]dB additional to that of the reference. The proposed circuit will occupy an area of 0.00064[Formula: see text]mm2 and offer a TC as low as 1.7077 ppm/∘C. The whole MOS approach facilitates a reduction in die area and process simplicity.

scholarly journals IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

2018 ◽  
Vol 8 (3) ◽  
pp. 1467 ◽  
Author(s):  
Maninder Kaur ◽  
Jasdeep Kaur
Keyword(s):  
Power Supply ◽  
Low Voltage ◽  
Fault Injection ◽  
Current Source ◽  
Cmos Technology ◽  
Injection Technique ◽  
Voltage Reference ◽  
Iddq Testing ◽  
Supply Current ◽  
Circuit Under Test

The paper describes the design for testability (DFT) of low voltage two stage operational transconductance amplifiers based on quiescent power supply current (IDDQ) testing. IDDQ testing refers to the integral circuit testing method based upon measurement of steady state power supply current for testing both digital as well as analog VLSI circuit. A built in current sensor, which introduces insignificant performance degradation of the circuit-under-test, has been proposed to monitor the power supply quiescent current changes in the circuit under test. Moreover, the BICS requires neither an external voltage reference nor a current source and able to detect, identify and localize the circuit faults. Hence the BICS requires less area and is more efficient than the conventional current sensors. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. Both bridging and open faults have been analyzed in proposed work by using n-well 0.18µm CMOS technology.

scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
pp. 1-6
Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

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