scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

scholarly journals A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2033
Author(s):  
Ahmed Elgreatly ◽  
Ahmed Dessouki ◽  
Hassan Mostafa ◽  
Rania Abdalla ◽  
El-sayed El-Rabaie
Keyword(s):  
Power Consumption ◽  
Software Defined Radio ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Analog To Digital Converters ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Operation Speed

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

A NOVEL DECOMPOSITION APPROACH AND VLSI IMPLEMENTATION OF CHROMA INTERPOLATOR FOR H.264 ENCODERS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340025
Author(s):  
TENG WANG ◽  
LEI ZHAO ◽  
ZI-YI HU ◽  
ZHENG XIE ◽  
XIN-AN WANG
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Hardware Design ◽  
Cmos Technology ◽  
Vlsi Implementation ◽  
Clock Frequency ◽  
Hardware Cost ◽  
Decomposition Approach ◽  
Lower Power ◽  
Decomposition Scheme

In this paper, a novel decomposition approach and VLSI implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders are proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements (AEs) which are comprised of only adders. Four types of AEs are developed and a pipelining hardware design is proposed to conduct the chroma interpolation with great hardware reuse. The proposed design was prototyped within a Xilinx Virtex6 XC6VLX240T FPGA with a clock frequency as high as 245 MHz. The proposed design was also synthesized with SMIC 130 nm CMOS technology with a clock frequency of 200 MHz, which could support a real-time HDTV application with less hardware cost and lower power consumption.

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

A Digital Linear-Switching Hybrid Power Amplifier for Envelope Tracking Hybrid Supply Modulators

2017 ◽  
Vol 26 (10) ◽  
pp. 1750162
Author(s):  
Atefeh Salimi ◽  
Rasoul Dehghani ◽  
Abdolreza Nabavi
Keyword(s):  
Power Consumption ◽  
Power Amplifier ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Envelope Tracking ◽  
Power Efficient ◽  
Class Ab ◽  
Digital To Analog Converters ◽  
Digitally Controlled ◽  
Digital Block

A novel envelope modulator for envelope tracking RF power amplifier (PA) is presented in this paper. The proposed modulator consists of a parallel combination of analog class AB and digitally controlled hybrid PAs. The analog and digital class AB PAs are effective in both reducing the clock frequency and also static power dissipation, thus improving the efficiency of the modulator. On the other hand, lower clock frequencies result in simpler and more power-efficient digital to analog converters required in the architecture. The modulator digital block is evaluated with a 45[Formula: see text]nm CMOS technology. The overall power consumption of the digital block is around 76[Formula: see text]mW at 800[Formula: see text]MHz clock frequency. As an application, the designed digital block is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital block power consumption, is around 80.7% at an average 32[Formula: see text]dBm output power for a 5[Formula: see text]MHz input signal.

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC Converter for Implantable Devices

2019 ◽  
Vol 29 (01) ◽  
pp. 2050013
Author(s):  
Najmeh Cheraghi Shirazi ◽  
Abumoslem Jannesari ◽  
Pooya Torkzadeh
Keyword(s):  
Power Consumption ◽  
Transient Response ◽  
Output Voltage ◽  
Low Voltage ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Voltage Ripple ◽  
Body Biasing

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4.

Thermally Reliable Ultra-Low-Power Voltage Reference to Regulator Converter

2020 ◽  
pp. 2150024
Author(s):  
George M. Joseph ◽  
Emmanouel George ◽  
Prathyush S. Pramod ◽  
Zameel Nizam ◽  
S. Krishnapriya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Current Efficiency ◽  
Power Supply ◽  
Cmos Technology ◽  
Surveillance Systems ◽  
Voltage Reference ◽  
Power Budget ◽  
Line Load ◽  
Ultra Low Power

A regulated power supply with ultra-low-power consumption, high current efficiency, line, load and thermal stability is an essential part of any high precision electronic system with stringent power budget such as biomedical sensors or military surveillance systems. In this paper, we propose an ultra-low-power, MOSFET only, voltage reference to regulator convertor, proficient to work below 1 V with reduced power consumption. The proposed idea incorporates the provision to integrate any voltage reference module to a comparator-based circuit so as to transform it to a voltage regulator having similar temperature coefficient (TC) and line regulation as that of the interfaced voltage reference. It is also able to produce a reliable output accounting to load fluctuations. The circuit is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology using Cadence Virtuoso simulation suit. The complete circuit was found to draw a quiescent current of 319.9 pA with a notable current efficiency of 99.99997% at 27∘C on driving a load of 1[Formula: see text]mA along with a Power Supply Rejection Ratio (PSRR) of [Formula: see text][Formula: see text]dB additional to that of the reference. The proposed circuit will occupy an area of 0.00064[Formula: see text]mm2 and offer a TC as low as 1.7077 ppm/∘C. The whole MOS approach facilitates a reduction in die area and process simplicity.

scholarly journals Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1256
Author(s):  
Seyedehsomayeh Hatefinasab ◽  
Noel Rodriguez ◽  
Antonio García ◽  
Encarnacion Castillo
Keyword(s):  
Standard Deviation ◽  
Power Consumption ◽  
Threshold Voltage ◽  
Low Cost ◽  
Process Variations ◽  
Cmos Technology ◽  
Soft Error ◽  
Single Event ◽  
Power Delay Product ◽  
The Impact

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks

2015 ◽  
Vol 24 (07) ◽  
pp. 1550109
Author(s):  
Meilin Wan ◽  
Zhenzhen Zhang ◽  
Wang Liao ◽  
Kui Dai ◽  
Xuecheng Zou
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Single Phase ◽  
Cmos Technology ◽  
Operating Frequency ◽  
Low Power Consumption ◽  
Frequency Range ◽  
Differential Input ◽  
Operating Frequency Range ◽  
Simulation Results

A dual-modulus prescaler (divide-by-2/3) using complementary clocking NMOS-like blocks is presented in this paper. The prescaler can work properly for both differential and single phase input clocks. For differential input clocks, the prescaler achieves not only high operating frequency but also low power consumption since it consists of only five NMOS-like blocks. For single phase input clock, the operating frequency range is further expanded by utilizing a complementary clocks generator. Simulation results show that, in 180-nm standard CMOS technology, the proposed prescaler achieves operating frequency range of 1.7–9.0 GHz for differential input clocks and 0.5–10.2 GHz for single phase input clock. And the maximum power consumption from 1.8 V power supply is 0.92 mW and 1.32 mW for differential and single phase input clocks respectively.

scholarly journals On Mixed PTL/Static Logic for Low-power and High-speed Circuits

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 399-406 ◽  
Author(s):  
Geun Rae Cho ◽  
Tom Chen
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Logic Gates ◽  
Cmos Technology ◽  
Cmos Process ◽  
Test Cases ◽  
Static Structure ◽  
Average Delay ◽  
Power Delay Product ◽  
Static Logic

We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering. Our experimental results demonstrate that the proposed mixed PTL structure beats pure static structure and conventional PTL in 9 out of 15 test cases for either delay or power consumption or both in a 0.25 μm CMOS process. The average delay, power consumption, and power-delay product of the proposed structure for 15 test cases are 10% to 20% better of than the pure static implementations and up to 50% better than the conventional PTL implementations.

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