500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits

2017 ◽  
Vol 38 (10) ◽  
pp. 1429-1432 ◽  
Author(s):  
Hossein Elahipanah ◽  
Saleh Kargarrazi ◽  
Arash Salemi ◽  
Mikael Ostling ◽  
Carl-Mikael Zetterling
2019 ◽  
Vol 963 ◽  
pp. 832-836 ◽  
Author(s):  
Shuo Ben Hou ◽  
Per Erik Hellström ◽  
Carl Mikael Zetterling ◽  
Mikael Östling

This paper presents our in-house fabricated 4H-SiC n-p-n phototransistors. The wafer mapping of the phototransistor on two wafers shows a mean maximum forward current gain (βFmax) of 100 at 25 °C. The phototransistor with the highest βFmax of 113 has been characterized from room temperature to 500 °C. βFmax drops to 51 at 400 °C and remains the same at 500 °C. The photocurrent gain of the phototransistor is 3.9 at 25 °C and increases to 14 at 500 °C under the 365 nm UV light with the optical power of 0.31 mW. The processing of the phototransistor is same to our 4H-SiC-based bipolar integrated circuits, so it is a promising candidate for 4H-SiC opto-electronics on-chip integration.


Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.


Author(s):  
Carl M. Nail

Abstract Dice must often be removed from their packages and reassembled into more suitable packages for them to be tested in automated test equipment (ATE). Removing bare dice from their substrates using conventional methods poses risks for chemical, thermal, and/or mechanical damage. A new removal method is offered using metallography-based and parallel polishing-based techniques to remove the substrate while exposing the die to minimized risk for damage. This method has been tested and found to have a high success rate once the techniques are learned.


1993 ◽  
Vol 320 ◽  
Author(s):  
S. P. Murarka

ABSTRACTSilicides have found application as high conductivity, high temperature, and corrosion resistance materials that form good electrical contacts to silicon and good low resistivity cladding on polysilicon films used as gate metal. Of various silicides investigated in past CoSi2 offers several advantages including lowest resistivity, self-aligned formation, low lattice mismatch with silicon, stability in presence of dopants and on SiO2, Si3N4, or Sioxynitrides, and reliability to process temperatures ≤900°C even when used in thicknesses as thin as 50-60 nm. Thus, CoSi2 has found an application in VLSI and ULSI. In this paper, the properties, formation and processing, reliability, and applicability of CoSi2 will be reviewed. It will be shown that CoSi2 is only silicide that offers properties and reliability for continued use in sub-0.25 pm VLSI and ULSI integrated circuits.


2018 ◽  
Vol 924 ◽  
pp. 854-857
Author(s):  
Ming Hung Weng ◽  
Muhammad I. Idris ◽  
S. Wright ◽  
David T. Clark ◽  
R.A.R. Young ◽  
...  

A high-temperature silicon carbide power module using CMOS gate drive technology and discrete power devices is presented. The power module was aged at 200V and 300 °C for 3,000 hours in a long-term reliability test. After the initial increase, the variation in the rise time of the module is 27% (49.63ns@1,000h compared to 63.1ns@3,000h), whilst the fall time increases by 54.3% (62.92ns@1,000h compared to 97.1ns@3,000h). The unique assembly enables the integrated circuits of CMOS logic with passive circuit elements capable of operation at temperatures of 300°C and beyond.


1989 ◽  
Vol 25 (17) ◽  
pp. 1133 ◽  
Author(s):  
S.E. Nordquist ◽  
J.W. Haslett ◽  
F.N. Trofimenkoff

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