A 71dB DC Gain, 0.1% THD, 0.5-V Bulk-Driven Class-AB OTA Achieved by Novel CMFB Methods

Author(s):  
Yangxin Xiang ◽  
Saisai Jin ◽  
Yongzhen Chen ◽  
Jiangfeng Wu
Keyword(s):  
Class Ab ◽  
2016 ◽  
Vol 5 (4) ◽  
pp. 438-448 ◽  
Author(s):  
Seyed Mahmoud Anisheh ◽  
Hossein Shamsi
Keyword(s):  
Class Ab ◽  
Dc Gain ◽  

2021 ◽  
Vol 11 (4) ◽  
pp. 37
Author(s):  
Andrea Ballo ◽  
Salvatore Pennisi ◽  
Giuseppe Scotti

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz.


2016 ◽  
Vol 25 (11) ◽  
pp. 1650144 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour

In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.


2021 ◽  
pp. 105101
Author(s):  
Mihika Mahendra ◽  
Shweta Kumari ◽  
Maneesha Gupta ◽  
Ankur Sangal

2009 ◽  
Vol 18 (02) ◽  
pp. 339-350 ◽  
Author(s):  
SALVATORE PENNISI ◽  
SALVATORE DI FAZIO ◽  
TIZIANA SIGNORELLI ◽  
FRANCESCO PULVIRENTI

A transconductance operational amplifier specifically optimized for a switched-capacitor LCD column driver is presented. It exploits MOS transistors in subthreshold region and dissipates 670 nA at DC. Despite this extremely low quiescent current value, the amplifier exhibits a DC gain of about 80 dB, and a gain-bandwidth product and phase margin around 2 MHz and 70°, with a load capacitance of 500 fF. Besides, working in class AB, the solution provides a slew rate equal to 27 V/μs. With exception of the DC gain, these performances represent an improvement with respect to comparable solutions, and are obtained while halving the area occupation.


2019 ◽  
Vol 13 (5) ◽  
pp. 614-621 ◽  
Author(s):  
Seyed Mahmoud Anisheh ◽  
Hamed Abbasizadeh ◽  
Hossein Shamsi ◽  
Chitra Dadkhah ◽  
Kang‐Yoon Lee
Keyword(s):  
Class Ab ◽  
Dc Gain ◽  

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