Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias

This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.

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Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2016.7804387 ◽

2016 ◽

Cited By ~ 3

Author(s):

R.T. Doria ◽

R. Trevisoli ◽

M. de Souza ◽

M.A. Pavanello ◽

D. Flandre

Keyword(s):

Gate Bias ◽

Back Gate ◽

Current Mirrors ◽

Self Cascode ◽

P Type

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Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096513666201208102615 ◽

2020 ◽

Vol 13 ◽

Author(s):

Kai Zhang ◽

Weifeng Lü ◽

Peng Si ◽

Zhifeng Zhao ◽

Tianyu Yu

Keyword(s):

Monte Carlo ◽

Integrated Circuits ◽

Metal Oxide ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Gate Bias ◽

Cmos Inverter ◽

Back Gate ◽

Random Dopant Fluctuation ◽

Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

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