Tunable loop filter in fractional-N frequency synthesizer for wireless applications

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.

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Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

Journal of Electrical Engineering ◽

10.2478/jee-2019-0063 ◽

2019 ◽

Vol 70 (4) ◽

pp. 323-328

Author(s):

Dan-Dan Zheng ◽

Yu-Bin Li ◽

Chang-Qi Wang ◽

Kai Huang ◽

Xiao-Peng Yu

Keyword(s):

Frequency Synthesizer ◽

Frequency Tuning ◽

Supply Voltage ◽

Current Mode ◽

Cmos Technology ◽

Mode Frequency ◽

Loop Filter ◽

Silicon Area ◽

Power Efficient ◽

A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

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Notice of Violation of IEEE Publication Principles: A low reference spurs 1-5 GHz 0.13 μm CMOS frequency synthesizer using a fully-sampled feed-forward loop filter architecture

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2007.907171 ◽

2007 ◽

Vol 42 (11) ◽

pp. 2503-2514 ◽

Cited By ~ 10

Author(s):

Adrian Maxim

Keyword(s):

Frequency Synthesizer ◽

Loop Filter ◽

Feed Forward ◽

Feed Forward Loop ◽

Filter Architecture ◽

5 Ghz

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Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

Indonesian Journal of Electrical Engineering and Computer Science ◽

10.11591/ijeecs.v4.i2.pp397-405 ◽

2016 ◽

Vol 4 (2) ◽

pp. 397

Author(s):

P.N. Metange ◽

K. B. Khanchandani

Keyword(s):

Leakage Current ◽

High Performance ◽

Charge Pump ◽

Phase Locked Loop ◽

Loop Filter ◽

Phase Frequency Detector ◽

Analysis And Design ◽

Wireless Applications ◽

5 Ghz ◽

Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications. The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

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A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽

10.3390/electronics10020109 ◽

2021 ◽

Vol 10 (2) ◽

pp. 109

Author(s):

Youming Zhang ◽

Xusheng Tang ◽

Zhennan Wei ◽

Kaiye Bao ◽

Nan Jiang

Keyword(s):

Phase Noise ◽

Frequency Synthesizer ◽

Frequency Tuning ◽

Cmos Technology ◽

Voltage Controlled Oscillator ◽

Loop Filter ◽

Chip Area ◽

Loop Bandwidth ◽

Bandwidth Control ◽

Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

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