Thermal resistance, thermomechanical stress and thermal cycling endurance of silicon chips bonded with adhesives

Author(s):  
A. Bjorneklett ◽  
T. Tuhus ◽  
L. Halbo ◽  
H. Kristiansen
2009 ◽  
Vol 38 (12) ◽  
pp. 2470-2478 ◽  
Author(s):  
H.Y. Guo ◽  
J.D. Guo ◽  
J.K. Shang

2010 ◽  
Vol 2010 (HITEC) ◽  
pp. 000129-000135 ◽  
Author(s):  
Martin Lederer ◽  
Javad Zarbakhsh ◽  
Rui Huang ◽  
Thomas Detzel ◽  
Brigitte Weiss

Thermomechanical stresses in metallic films are a root cause for material fatigue which limits the lifetime of electronic devices. Since the yield stress of metals is temperature dependent, plastic deformations during thermal cycling are increased at elevated temperature. This effect reduces the reliability of electronic parts. In order to investigate this problem, a 20μm thick copper film was deposited on a silicon wafer. After annealing at 400°C, the sample was exposed to thermal cycles in the temperature range between room temperature and 600°C. The different values for the CTE of copper and silicon lead to a curvature of the sample. The wafer curvature was measured by a multi-laser beam method. On the basis of the experimental results, a new theoretical model was developed, which describes the stress evolution in the film during thermal cycling. In this investigation, the relation between wafer curvature and film stress is calculated by analogy to a model by Freund [1] which is an improvement to the well known Stoney formula. In addition to the elastic response, the new model considers plasticity of the copper film as well as temperature dependence of creep. It is demonstrated that the model can well describe the experiment and thus thermomechanical stress in copper films.


Author(s):  
Roy W. Knight ◽  
Yasser Elkady ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA’s was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from −40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. Finite element analysis identified critical thermal and perimeter solder balls as the most likely sites for cracking. Boards were cross-sectioned and examined for solder joint cracks and delamination to identify the cause for the observed increases in thermal resistance. Cracking was found in the critical thermal and perimeter solder balls.


2016 ◽  
Vol 28 (4) ◽  
pp. 177-187
Author(s):  
Mei-Ling Wu ◽  
Jia-Shen Lan

Purpose This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs). Design/methodology/approach This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace’s equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package. Findings This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package. Research limitations/implications Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed. Practical implications The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board. Social implications In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model. Originality/value The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.


2010 ◽  
Vol 7 (2) ◽  
pp. 99-104 ◽  
Author(s):  
Martin Lederer ◽  
Javad Zarbakhsh ◽  
Rui Huang ◽  
Thomas Detzel ◽  
Brigitte Weiss

Thermomechanical stresses in metallic films are a root cause for material fatigue which limits the lifetime of electronic devices. Since the yield stress of metals is temperature dependent, plastic deformations during thermal cycling are increased at elevated temperature. This effect reduces the reliability of electronic parts. In order to investigate this problem, a 20 μm thick copper film was deposited on a silicon wafer. After annealing at 400°C, the sample was exposed to thermal cycles in the temperature range between room temperature and 600°C. The different values for the coefficient of thermal expansion of copper and silicon lead to a curvature of the sample. The wafer curvature was measured by a multilaser beam method. On the basis of the experimental results, a new theoretical model was developed that describes the stress evolution in the film during thermal cycling. In this investigation, the relation between wafer curvature and film stress is calculated by analogy to a model by Freund which is an improvement to the well-known Stoney formula. In addition to the elastic response, the new model considers plasticity of the copper film as well as temperature dependence of creep. It is demonstrated that the model can describe the experiment well and thus thermomechanical stress in copper films.


2008 ◽  
Vol 59 ◽  
pp. 143-147
Author(s):  
Svetlana Levchuk ◽  
Monika Poebl ◽  
Gerhard Mitic

In view of power electronics applications, baseplates made from metal diamond composites have been manufactured and characterised. The surface contours of the baseplates were measured during thermal loads up to 180°C starting at room temperature with help of the TherMoiré technique. X-ray analysis investigation was performed to detect porosity and local inhomogeneities of the baseplates. Al- and Cu-based diamond composite baseplates were Ni-plated and used for manufacturing of 3.3 kV IGBT modules. The solder layer between AlN AMB (active metal brazing) substrates and baseplates was investigated by ultrasonic and X-Ray analyses. Thermal resistance of the manufactured IGBT modules was characterised and compared to that of IGBT modules with AlSiC or Cu baseplates. The influence of thermal cycling on the solder layer and thermal resistance of the manufactured module was investigated.


Author(s):  
Amy S. Fleischer ◽  
Barry C. Johnson ◽  
Li-Hsin Chang

During semiconductor manufacturing, voids are easily formed in the die attach bond layer and are found to form, grow and coalesce with thermal cycling. The presence of such voids is known to adversely affect the package thermal resistance, but to this point, not enough data exists to precisely analyze the effects of void size, configuration and depth. Using an innovative experimental method the present study investigates these effects with a carefully controlled void geometry. The results show that the thermal resistance increases linearly with void percentage for random voids, but increases exponentially for contiguous voids.


Author(s):  
Rajesh Tripathi ◽  
Sejin Im ◽  
Douglas Devoto ◽  
Joshua Major ◽  
Sreekant Narumanchi ◽  
...  

Increased adoption of hybrid and electrical vehicles as well as renewable energy systems are driving the innovation in power module packaging. Thermal substrate, one of the major components of power modules, is not an exception, and technological advancements are necessary to meet increased reliability requirements. DuPont has developed a thermally conductive polymer film that provides very low thermal resistance and very high insulation. The film can be bonded to conductive and thick metallic layers and this polymer equivalent of DBC shows very high reliability in addition to high performance characteristics. Electrically insulating layers within a power electronics module are critical for separating circuitry from thermal management layers. Electrical insulating substrates typically used in power electronics modules utilize a ceramic layer, comprised most commonly of either Al2O3, AlN, or Si3N4. Thin Cu layers are bonded to either side of the substrate using a direct bond Cu (DBC) or active metal brazing (AMB) process. These processes involve bonding metallization layers to both sides of the ceramic at a high temperature as bonding to only one side would cause deformation during the cooling phase. Typical metal thickness bonded to either side of the ceramic is about 0.3–0.6 mm as the high temperature manufacturing process does not allow very thick metals to be bonded and this limits the heat spreading capability of the thermal substrate. DuPont's new Temprion™ Organic Direct Bond Copper (ODBC) address aforementioned problems, increasing thermal durability and reliability as well as enabling system layer suppression. Temprion™ ODBC's dielectric layer will absorb thermo-mechanical stress from the metals due to CTE mismatch, dramatically improving durability of the system. In addition, various kinds of metals including Cu and Al can be easily bonded to Temprion™ DB films through simple process. There are no thickness limitations on bonding metal sheets and metal attached at the bottom can be used as an integrated heat sink/baseplate. Al2O3 and Si3N4-based substrates were utilized as a baseline for reliability comparison with the DuPont substrates. The industry-standard substrates in used in this study have a thickness of 0.3 and 0.8 mm for the Cu metallization layers and 0.38 and 0.32 mm for the insulating layer respectively for Al2O3 an Si3N4 insulators. DuPont ODBC substrates were fabricated by attaching a polyimide layer to a layer of 0.8-mm-thick Cu. The polyimide and bottom Cu layer cross-sectional footprints are both 50.8 mm × 50.8 mm. The corners of both layers were filleted with various radii (0.5, 1.0, 2.0, and reversed 2.0 mm) to explore the impact of different stress concentrations between the metallization and insulating layers. The top Cu metallization was inset 2.0 mm from the perimeter of the electrically-insulating substrate and bottom Cu metallization.10 samples each of the DuPont ODBC and industry Al2O3 substrates were placed in a thermal shock chamber and cycled between temperature extremes of −40°C and 200°C. Substrates were inspected every 1000 cycles. After 5000 cycles, the ODBC substrates experienced no hipot failures, but preliminary edge delamination was visually observed. Al2O3 substrates all failed after 50 thermal cycles.Five DuPont ODBC samples were placed in a thermal chamber and subjected to an elevated temperature of 175°C. After 2000 hours, no hipot failures were observed, but edge delamination was again observed.Five DuPont ODBC samples were attached to a cold plate with Kapton tape. Heater cartridges were attached to the top of the substrates with Kapton tape and thermocouples were placed in several locations through the package. The heater cartridges were alternated between on and off states to allow for the substrates to cycle between −40°C and +200°C. While the change between the maximum and minimum temperatures is smaller for the power cycling test compared to the thermal cycling test, the heater cartridge and cold plate create a thermal gradient within the samples that is not possible with passive thermal cycling. After 2000 hrs cycles of testing, no hipot failures or edge delamination have been observed. Herein we show that the DuPont ODBC substrate design is a promising alternative to traditional industry substrates based on ceramic insulators. The reliability of the substrate design has been demonstrated under several thermomechanical accelerated tests and the electrical and thermal performance has been measured. Future work will include reliability comparisons to other industry substrates, including thermal shock testing of substrates with HPS, AlN, and Si3N4 ceramic layers. Thermal models will correlate thermal resistance values measured by the transient thermal tester and compare the ODBC substrate performance to industry substrates within a commercialized power electronics module. The modeling will also optimize the thickness of the metallization layers within the ODBC substrates to minimize the junction temperature of the switching devices.


Sign in / Sign up

Export Citation Format

Share Document