Development of 3D Wafer Level Packaging for SAW Filters Using Thin Glass Capping Technology

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

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Thin Glass Handling Solutions for Microelectronics Packaging

International Symposium on Microelectronics ◽

10.4071/2380-4505-2020.1.000192 ◽

2020 ◽

Vol 2020 (1) ◽

pp. 000192-000196

Author(s):

Aric Shorey ◽

Shelby Nelson ◽

David Levy ◽

Paul Ballentine

Keyword(s):

Wafer Level ◽

Microelectronics Packaging ◽

Thin Glass ◽

Glass Substrates ◽

Wafer Level Packaging ◽

Fine Pitch ◽

Temporary Bonding ◽

Bonding Technology ◽

Rf Loss ◽

Grinding Operations

Abstract Glass substrates with fine-pitch through-glass via (TGV) technology gives an attractive approach to wafer level packaging and systems integration. Glass can be made in very thin sheets (<100 um thick) which aids in integration and eliminates the need for back-grinding operations. Electrical and physical properties of glass have many attractive attributes such as low RF loss, the ability to adjust thermal expansion properties, and low roughness with excellent flatness to achieve fine L/S. Furthermore, glass can be fabricated in panel format to reduce manufacturing costs. The biggest challenge to adopting glass as a packaging substrate has been the existence of gaps in the supply chain, caused primarily by the difficulty in handling large, thin glass substrates using standard automation and processing equipment. This paper presents a temporary bonding technology that allows the thin glass substrates to be processed in a semiconductor fab environment without the need to modify existing equipment.

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Wafer-level packaging for ultra-thin glasses using hermetic room temperature welding technology

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2016dpc-tha44 ◽

2016 ◽

Vol 2016 (DPC) ◽

pp. 002203-002221 ◽

Cited By ~ 1

Author(s):

Heidi Lundén ◽

Antti Peltonen ◽

Antti Määttänen

Keyword(s):

Heat Load ◽

Adhesive Bonding ◽

Wafer Level ◽

Thin Glass ◽

Wafer Level Packaging ◽

Welding Technology ◽

Direct Laser ◽

Additive Materials ◽

Manufacturing Technologies ◽

Glass Packaging

The aim of the study was to develop a hermetic package using ultra-thin glass wafers. A novel glass welding technology, with a minimal heat load, was used to construct the encapsulations. Industry requirements of the miniaturization of the electronic components, for example in medical implants and consumer electronics and opto-electronics, challenge the conventional manufacturing technologies and package materials [1]. Low-cost glass interposers and packages have been research by GeorgiaTech at their PRC industry program. Glass packaging can offer even ten times affordable option than using silicon [2]. During the last few years, the advancements in the glass manufacturing technologies have enabled a cost effective production of the ultra-thin glass wafers and panels. Laborious glass grinding process from thick material to ultra-thin is no longer necessary since the fusion forming process can be used. Ultra-thin glass makes it possible to reduce the package size and weight [3]. Typically, glasses thickness of 300 μm or less are considered as ultra-thin material. However, even as thin as 25 μm glass is commercially available [4]. Several methods are used for glass joining including: anodic, fusion, and adhesive bonding [5]. During the recent years increasing number of laser based techniques are applied to glass packaging. Numerous studies have concentrated on frit bonding [6, 7]. Elementary study of the direct laser joining without any additive layers has been demonstrated by Miyamoto et al. [8]. Glass welding method has been further investigated in several researches [9, 10]. The package is constructed of three ultra-thin glass wafers: base and lid, thicknesses of 200 μm and spacer, thickness of 100 μm. Commercially available 6” borosilicate, D263T, wafers are used which were welded together by using novel laser welding technology. Welding is implemented on material interface without using any additive materials or coating layers. Glass surfaces are left untouched and optical quality is retained. Welding was performed on a wafer level and the single packages were cut after the final welding. Hermeticity test was performed to ensure the welding quality. Radioisotope leak test with krypton 85 was performed at Oneida Research Services. The results showed an excellent hermeticity: leak rate less than 6,0×10–12 atmcm3/s Kr-85 was achieved. Limits set in the MIL-standard are easily reached. The study proves that novel glass welding technology can be applied to wafer-level packaging with ultra-thin glasses. Technique eliminates the need of additive materials, and due to the minimal heat load bending and warping of the material can be avoided. Also, glass offers effortless visual inspection through the entire lifetime of the device.

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MEMS Wafer-level Packaging Technology Using LTCC Wafer

IEEJ Transactions on Sensors and Micromachines ◽

10.1541/ieejsmas.132.246 ◽

2012 ◽

Vol 132 (8) ◽

pp. 246-253 ◽

Cited By ~ 1

Author(s):

Mamoru Mohri ◽

Masayoshi Esashi ◽

Shuji Tanaka

Keyword(s):

Wafer Level ◽

Packaging Technology ◽

Wafer Level Packaging

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3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0033 ◽

2014 ◽

Author(s):

A. Orozco ◽

N.E. Gagliolo ◽

C. Rowlett ◽

E. Wong ◽

A. Moghe ◽

...

Keyword(s):

Magnetic Field ◽

Fault Isolation ◽

Wafer Level ◽

Wafer Level Packaging ◽

Current Location ◽

Geometrical Information ◽

Magnetic Field Imaging ◽

Silicon Vias ◽

Non Destructive ◽

Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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