Thin-Gate-Oxide Breakdown and CPU Failure-Rate Estimation

2007 ◽  
Vol 7 (1) ◽  
pp. 74-83 ◽  
Author(s):  
Yung-Huei Lee ◽  
Neal R. Mielke ◽  
William McMahon ◽  
Yin-Lung Ryan Lu ◽  
Sangwoo Pae
2010 ◽  
Vol 57 (9) ◽  
pp. 2296-2305 ◽  
Author(s):  
David F. Ellis ◽  
Yuanzhong Zhou ◽  
Javier A. Salcedo ◽  
Jean-Jacques Hajjar ◽  
Juin J. Liou

2001 ◽  
Vol 40 (Part 2, No. 12A) ◽  
pp. L1286-L1289 ◽  
Author(s):  
Hyun-Soo Kim ◽  
Ki-Sang Lee ◽  
Bo-Young Lee ◽  
Hak-Do Yoo ◽  
Seung-Ho Pyi ◽  
...  

2014 ◽  
Vol 696 ◽  
pp. 57-61
Author(s):  
Ling Sun ◽  
Yu Wei Zhou ◽  
Hong Wang ◽  
Xiang Dong Luo ◽  
Jia Yuan Guo

The relationship between the location of gate oxide breakdown in n-MOSFETs and its electrical characteristics has been studied by using TCAD software. The comparison of device terminal current with gate oxide breakdown at different locations suggests that the variation of the source and the drain currents can be directly correlated to the breakdown location in the ultra thin gate oxide. The results provide a fundamental understanding to the experimental results observed in our devices.


Author(s):  
Yung-huei Lee ◽  
Neal Mielke ◽  
Marty Agostinelli ◽  
Sukirti Gupta ◽  
Ryan Lu ◽  
...  

2002 ◽  
Vol 12 (3) ◽  
pp. 57-60 ◽  
Author(s):  
B. Cretu ◽  
F. Balestra ◽  
G. Ghibaudo ◽  
G. Guégan

Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.


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