scholarly journals NANO-MOSFETs IMPLEMENTATION OF DIFFERENT LOGIC FAMILIES OF TWO INPUTS NAND GATE TRANSISTOR LEVEL CIRCUITS: A SIMULATION STUDY

2017 ◽  
Vol 79 (7) ◽  
Author(s):  
Ooi Chek Yee ◽  
Lim Soo King
Keyword(s):  
Simulation Study ◽  
High Speed ◽  
Transient Analysis ◽  
Channel Length ◽  
Nand Gate ◽  
Timing Diagrams ◽  
Modeling Calculation ◽  
P Type ◽  
Transistor Circuit ◽  
Nano Mosfet

In this paper, simulation study has been carried out on two inputs logic NAND transistor circuits with four different logic families, namely (i) nano-CMOS NAND gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NAND gate, (iii) resistive loaded nano-MOSFET NAND gate, and (iv) pseudo nano-MOSFET NAND gate. The simulation tool used is WinSpice. All the n-type and p-type nano-MOSFETs have channel length (L) 10 nm with width (W) 125 nm or 250 nm, depending on type of logic families. The problem with downscaling of nano-MOSFET is the implementation of low power high speed nano-MOSFET transistor circuit. Simulated timing diagrams for input and output waveforms showed correct logical NAND gate operations for all four logic families. Transient analysis on nano-MOSFET loaded n-type nano-MOSFET NAND gate shows that theoretical modeling calculation of rise time (tr), fall time (tf) and maximum operating frequency (fmax) are reasonably matched simulated output result of WinSpice. All the logic family circuits studied shown reduction in dynamic power when MOSFET is downscaled to nanometer regime.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Simulation study of Landau damping near the persisting to arrested transition

2017 ◽  
Vol 83 (4) ◽  
Author(s):  
Alexander J. Klimas ◽  
Adolfo F. Viñas ◽  
Jaime A. Araneda
Keyword(s):  
Phase Space ◽  
Simulation Study ◽  
High Speed ◽  
Space Distribution ◽  
Landau Damping ◽  
Field Mode ◽  
Low Speed ◽  
Phase Space Distribution ◽  
Saturation Stage ◽  
First Time

A one-dimensional electrostatic filtered Vlasov–Poisson simulation study is discussed. The transition from persisting to arrested Landau damping that is produced by increasing the strength of a sinusoidal perturbation on a background Vlasov–Poisson equilibrium is explored. Emphasis is placed on observed features of the electron phase-space distribution when the perturbation strength is near the transition value. A single ubiquitous waveform is found perturbing the space-averaged phase-space distribution at almost any time in all of the simulations; the sole exception is the saturation stage that can occur at the end of the arrested damping scenario. This waveform contains relatively strong, very narrow structures in velocity bracketing $\pm v_{\text{res}}$ – the velocities at which electrons must move to traverse the dominant field mode wavelength in one of its oscillation periods – and propagating with $\pm v_{\text{res}}$ respectively. Local streams of electrons are found in these structures crossing the resonant velocities from low speed to high speed during Landau damping and from high speed to low speed during Landau growth. At the arrest time, when the field strength is briefly constant, these streams vanish. It is conjectured that the expected transfer of energy between electrons and field during Landau growth or damping has been visualized for the first time. No evidence is found in the phase-space distribution to support recent well-established discoveries of a second-order phase transition in the electric field evolution. While trapping is known to play a role for larger perturbation strengths, it is shown that trapping plays no role at any time in any of the simulations near the transition perturbation strength.

scholarly journals High-speed operation in printed organic inverter circuits with short channel length

2014 ◽  
Vol 15 (11) ◽  
pp. 2696-2701 ◽  
Author(s):  
Yudai Yoshimura ◽  
Yasunori Takeda ◽  
Kenjiro Fukuda ◽  
Daisuke Kumaki ◽  
Shizuo Tokito
Keyword(s):  
High Speed ◽  
Channel Length ◽  
Short Channel ◽  
Organic Inverter

scholarly journals Enabling high-speed wide-field dynamic imaging in multifocal photoacoustic computed microscopy: a simulation study

2016 ◽  
Vol 55 (14) ◽  
pp. 3724 ◽  
Author(s):  
Hongying Wan ◽  
Yihang Zhou ◽  
Leslie Ying ◽  
Jing Meng ◽  
Liang Song ◽  
...  
Keyword(s):  
Simulation Study ◽  
High Speed ◽  
Dynamic Imaging ◽  
Wide Field ◽  
Field Dynamic
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