scholarly journals High-speed operation in printed organic inverter circuits with short channel length

2014 ◽  
Vol 15 (11) ◽  
pp. 2696-2701 ◽  
Author(s):  
Yudai Yoshimura ◽  
Yasunori Takeda ◽  
Kenjiro Fukuda ◽  
Daisuke Kumaki ◽  
Shizuo Tokito
Keyword(s):  
High Speed ◽  
Channel Length ◽  
Short Channel ◽  
Organic Inverter

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Design and Characterization of the Next Generation Nanowire Amplifiers

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-5
Author(s):  
Sotoudeh Hamedi-Hagh ◽  
Ahmet Bindal
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Next Generation ◽  
Short Channel ◽  
Surrounding Gate ◽  
Channel Effects ◽  
Gate Control ◽  
Voltage Swing

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.

SLD-MOSCNT: A new MOSCNT with step–linear doping profile in the source and drain regions

2017 ◽  
Vol 31 (01) ◽  
pp. 1650242 ◽  
Author(s):  
Behrooz Abdi Tahne ◽  
Ali Naderi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Cutoff Frequency ◽  
Basic Structure ◽  
Channel Length ◽  
Doping Profile ◽  
Horizontal Distance ◽  
Short Channel ◽  
Channel Effects ◽  
Channel Lengths

In this paper, a new structure, step–linear doping MOSCNT (SLD-MOSCNT), is proposed to improve the performance of basic MOSCNTs. The basic structure suffers from band to band tunneling (BTBT). We show that using SLD profile for source and drain regions increases the horizontal distance between valence and conduction bands at gate to source/drain junction which reduces BTBT probability. SLD performance is compared with other similar structures which have recently been proposed to reduce BTBT such as MOSCNT with lightly-doped drain and source (LDDS), and with double-light doping in source and drain regions (DLD). The obtained results using a nonequilibrium Green’s function (NEGF) method show that the SLD-MOSCNT has the lowest leakage current, power consumption and delay time, and the highest current ratio and voltage gain. The ambipolar conduction in the proposed structure is very low and can be neglected. In addition, these structures can improve short-channel effects. Also, the investigation of cutoff frequency of the different structures shows that the SLD has the highest cutoff frequency. Device performance has been investigated for gate length from 8 to 20 nm which demonstrates all discussions regarding the superiority of the proposed structure are also valid for different channel lengths. This improvement is more significant especially for channel length less than 12 nm. Therefore, the SLD can be considered as a candidate to be used in the applications with high speed and low power consumption.

Short-channel and high-mobility p- and n-type organic single-crystal transistors with air-gap structures

2012 ◽  
Vol 1402 ◽  
Author(s):  
M. Uno ◽  
T. Uemura ◽  
K. Miwa ◽  
A. Facchetti ◽  
J. Takeya
Keyword(s):  
Single Crystal ◽  
High Speed ◽  
Carrier Mobility ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Channel Length ◽  
Air Gap ◽  
Short Channel ◽  
Glass Substrates ◽  
Channel Lengths

ABSTRACTIn an effort to realize high-speed organic logic components, p- and n-type single-crystal organic field-effect transistors (SC-OFETs) were fabricated using air-gap structures with channel lengths as short as several μm. High carrier mobility of about 10 cm2/Vs is demonstrated in rubrene SC-OFETs even with the short channel length of 6 μm, using Si-based microstructures. The contact resistance is estimated to be 450 Ohm cm, which is only 5% of the total channel resistance between source and drain electrodes. Performances of n-type air-gap devices based on PDIF-CN2 are also demonstrated exhibiting electron transport with the carrier mobility of about 2 cm2/Vs. Furthermore, micron-scale air-gap structures are fabricated using insulating materials on glass substrates to reduce parasitic gate capacitance. The cut-off frequency of this rubrene air-gap device is measured to be as high as 8 MHz with applied drain voltage VD of 15 V. These techniques are promising to be applicable to next-generation organic high-speed logic circuits.

Characteristics of Sub-micron Polysilicon Thin Film Transistors

1994 ◽  
Vol 345 ◽  
Author(s):  
Kola R Olasupo ◽  
Professor M. K. Hatalis
Keyword(s):  
Thin Film ◽  
Leakage Current ◽  
High Speed ◽  
Thin Film Transistor ◽  
Random Access ◽  
Channel Length ◽  
Large Area ◽  
Short Channel ◽  
Active Matrix ◽  
Static Random Access Memories

AbstractThe polysilicon thin film transistor has been actively studied for the large area display applications like active matrix liquid crystal displays and for load cell in static random access memories. Due to low effective carrier mobility in polysilicon, the circuit speed is limited. Since the circuit delay time is directly proportional to the square of the channel length, short channel TFTs will be advantageous for high speed applications. In this work, we have studied the current voltage characteristics of an inverted sub-micron P-channel polysilicon thin-film transistor with self-aligned LDD structure to obtain a well-controlled channel and drain offset lengths. The particular features we examined are the leakage current and mobility. The leakage current and the ON current were found to be in the picoamp and micro-amp range respectively for devices having channel length in the range of 1.0μm to 0.35μm. Even very small devices having L&W = 0.35μm × 0.35μm exhibited characteristics similar to wider devices. The on/off current ratio was in the order of 105 before hydrogenation.

Influence of Channel Length and High-K Oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate Stack DG-MOSFETs

NANO ◽  
2016 ◽  
Vol 11 (09) ◽  
pp. 1650101 ◽  
Author(s):  
Sarosij Adak ◽  
Sanjit Kumar Swain ◽  
Arka Dutta ◽  
Hafizur Rahaman ◽  
Chandan Kumar Sarkar
Keyword(s):  
High Speed ◽  
Oxide Thickness ◽  
Channel Length ◽  
Gate Stack ◽  
Short Channel ◽  
Power Circuit ◽  
Novel Device ◽  
High K ◽  
Channel Effects ◽  
High Speed Switching

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), [Formula: see text]/[Formula: see text], [Formula: see text] roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

Hot Carrier Effects in Deep Submicron Nmosfets

1996 ◽  
Vol 428 ◽  
Author(s):  
Abhijit Phanse ◽  
Samar Saha
Keyword(s):  
Electric Fields ◽  
Channel Length ◽  
Deep Submicron ◽  
Short Channel ◽  
Hot Carrier ◽  
Velocity Saturation ◽  
Substrate Current ◽  
Hot Carrier Effects ◽  
Saturation Effects ◽  
Channel Lengths

AbstractThis paper addresses hot-carrier related reliability issues in deep submicron silicon nMOSFET devices. In order to monitor the hot-carrier induced device degradation, the substrate current was measured for devices with varying channel lengths (20 um - 0.24 um) under various biasing conditions. Deep submicron devices experience velocity saturation of channel carriers due to extremely high lateral electric fields. To evaluate the effects of velocity saturation in the channel, the pinch-off length in the channel was extracted for all the devices of the target technology. It was observed that for very short channel devices, carriers in most of the channel experience velocity saturation and almost the entire channel gets pinched off. It is shown in this paper that for very short channel devices, the pinch-off length in the channel is limited by the effective channel length, and that velocity saturation effects are critical to the transport of channel carriers.

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

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