Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs Shaded Conditions

2020 ◽  
Vol 24 (1) ◽  
Author(s):  
Rekib Uddin Ahmed ◽  
Prabir Saha
Keyword(s):  
Integrated Circuits ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Cmos Technology ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
Analytical Models ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects

Nowadays, the endlessly increasing demand for faster and complex integrated circuits (IC) has been fuelled by the scaling of metal-oxide-semiconductor field-effect-transistors (MOSFET) to smaller dimensions. The continued scaling of MOSFETs approaches its physical limits due to short-channel effects (SCE). Double-gate (DG) MOSFET is one of the promising alternatives as it offers better immunity towards SCEs and can be scaled to the shortest channel length. In future, ICs can be designed using DG-CMOS technology for which mathematical models depicting the electrical characteristics of the DG MOSFETs are foremost needed. In this paper, a review on n-type symmetric DG MOSFETs models has been presented based on the analyses of electrostatic potential distribution, threshold voltage, and drain-current models. Mathematical derivations of the device models are described elaborately, and numerical simulations are also carried out to validate the replicability of models.

Examining the Short Channel Characteristic and Performance of Triple Material Double Gate Silicon-on-Nothing Metal Oxide Semiconductor Field Effect Transistors with Grading Channel Concentration

2019 ◽  
Vol 14 (12) ◽  
pp. 1672-1679 ◽  
Author(s):  
Ningombam Ajit Kumar ◽  
Aheibam Dinamani Singh ◽  
Nameirakpam Basanta Singh
Keyword(s):  
Surface Potential ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel Effects ◽  
Parabolic Approximation ◽  
Short Channel ◽  
Channel Characteristic ◽  
Channel Effects ◽  
And Performance

A 2D surface potential analytical model of a channel with graded channel triple material double gate (GCTMDG) Silicon-on-Nothing (SON) MOSFET is proposed by intermixing the benefits of triple material in gate engineering and graded doping in the channel. The surface potential distribution function of the GCTMDG SON MOSFET is obtained by solving the Poisson's equation, applying suitable boundary conditions, and using a parabolic approximation method. It is seen in the proposed device that the Short Channel Effects (SCEs) are subdued due to the apprehensible step in the surface potential profile that screen the potential of the drain. The effects of the various device parameters are studied to check the merit of the device. For the validation of the proposed device, it is compared with the simulated results of ATLASTM, a device simulator from SILVACO.

scholarly journals Design and Characterization of the Next Generation Nanowire Amplifiers

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-5
Author(s):  
Sotoudeh Hamedi-Hagh ◽  
Ahmet Bindal
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Next Generation ◽  
Short Channel ◽  
Surrounding Gate ◽  
Channel Effects ◽  
Gate Control ◽  
Voltage Swing

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.

scholarly journals Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs

2021 ◽  
Vol 7 (1) ◽  
pp. 18-29
Author(s):  
Vinod Pralhad Tayade ◽  
Swapnil Laxman Lahudkar
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
20 Nm ◽  
Graphene Material

In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

scholarly journals Impact of Variation of Device Parameters on the Electrical Characteristics of Double-Gate Mosfets

2020 ◽  
Vol 9 (3) ◽  
pp. 3658-3661
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Channel Effects ◽  
Circuits Vlsi ◽  
Logical Functions

Very large scale integrated circuits (VLSI) have been possible owing to the shrinking of metal-oxide semiconductor field-effect transistors (MOSFETs). By reducing the dimensions of the device it is possible to have high density on the chip. This increases the number of logical functions that can be implemented on a given dimension of the chip. Along with the advantages associated with the shrinking of the devices, it also has certain drawbacks commonly known as short-channel effects. Due to these effects, device characteristics deviate from its expected values. There are many techniques through which these deviations can be minimized. One of the promising and highly researched techniques these days is the use of Multi-gate (MG) transistors in VLSI. Double-gate (DG) transistor is one among MG transistors. In DG MOSFET, substrate is surrounded by gates from two opposite sides. This leads to more control over the channel electrons by the gate terminals. In this paper, the consequence of change of various device constraints on the electrical characteristics of the DG MOSFETs will be investigated. Through the results, one can know to what extent the electrical properties changes when the dimensions and/or material properties are changed. This will be very helpful in determining the maximum current associated with those dimensions of DG MOSFETs.

scholarly journals Improvements in FOMs and Thermal Effects of a III-V Compound Material Based Short- Channel Thin Film Junctionless Double Gate MOSFETs

2021 ◽  
Author(s):  
Soumendra Kumar Rout ◽  
Pradipta Dutta
Keyword(s):  
Dielectric Material ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
Injection Velocity ◽  
Double Gate ◽  
Short Channel ◽  
K Value ◽  
Compound Material ◽  
Silicon Based

Abstract Better figure of merits (FOMs) have been achieved by using III-V compound material based junctionless double gate metal-oxide semiconductor field-effect transistors (JL DG-MOSFETs), and a thorough analysis of the device's performance over temperature has been performed using a highly N-doped GaAs-based JL DG-MOSFET using III-V compound material GaSb. GaSb, a compound material, is employed as the source material, which is well known for its greater mobility and injection velocity property with GaAs as the channel and drain materials, to obtain more output current and less leakage current due to the development of hetero structure (GaSb-GaAs) at the source-channel interface. The dielectric material HfO2 with a high k value is utilized to reduce the gate tunneling effects of electrons and enhance the control of the gate at the 20 nm channel length. Primary and auxiliary gates are taken to include ipact ionization on drain side for reducing the Subthreshold-swing. Numerous characteristics of a DG JLMOSFET, such as Id, SS, gm, TGF, Ion / Ioff, Cgs, and fT, GFP, TFP, GTFP are explored and compared with a silicon based material. The proposed structure shows an improved results comparing to the earlier model with Id of 117 mA, SS of 15.08 mV/decade, gm of 0.62 A/V, TGF of 38.8 V-1, Ion / Ioff ratio of 1.89 x 10 13, Cgs of 5.86 x 10 -16 F, fT of 2.05 x 10 15 Hz, GTFP of 1.81 x 10 17 Hz/V for the improvement of FOM in RF and DC analysis

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