Numerical simulation of Gate shape effect on Self-Heating in nano-MOSFET Transistors with high-k dielectric

The aim of the present work is to investigate numerically the self-heating effect (SHE) in MOSFET transistors based on high-k material taking into account the deformation of the gate under the SHE. The SHE inside the MOSFET transistor is calculated using the electrothermal model based on heat transfer equation coupled with semiconductor equations. The electrothermal model have been solved in 2D-dimension using the finite element method. The high-k dielectric HfO2 have been used as gate oxide. Several gate shapes have been used to analyze their impact on SHE. It is observed that the reduction of equivalent oxide thickness (EOT) reduces the SHE in the MOSFET transistor based in high-k dielectric material. the temperature peak increases quadratically with drain voltage for all MOSFET structures. A decrease in self-heating effect is achieved using the square gate shape.

NANO-MOSFETs IMPLEMENTATION OF DIFFERENT LOGIC FAMILIES OF TWO INPUTS NAND GATE TRANSISTOR LEVEL CIRCUITS: A SIMULATION STUDY

In this paper, simulation study has been carried out on two inputs logic NAND transistor circuits with four different logic families, namely (i) nano-CMOS NAND gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NAND gate, (iii) resistive loaded nano-MOSFET NAND gate, and (iv) pseudo nano-MOSFET NAND gate. The simulation tool used is WinSpice. All the n-type and p-type nano-MOSFETs have channel length (L) 10 nm with width (W) 125 nm or 250 nm, depending on type of logic families. The problem with downscaling of nano-MOSFET is the implementation of low power high speed nano-MOSFET transistor circuit. Simulated timing diagrams for input and output waveforms showed correct logical NAND gate operations for all four logic families. Transient analysis on nano-MOSFET loaded n-type nano-MOSFET NAND gate shows that theoretical modeling calculation of rise time (tr), fall time (tf) and maximum operating frequency (fmax) are reasonably matched simulated output result of WinSpice. All the logic family circuits studied shown reduction in dynamic power when MOSFET is downscaled to nanometer regime.