Solving Thermal Issues in a Three-Dimensional-Stacked-Quad-Core Processor by Microprocessor Floor Planning, Microchannel Cooling, and Insertion of Through-Silicon-Vias

2013 ◽  
Vol 135 (4) ◽  
Author(s):  
Anjali Chauhan ◽  
Bahgat Sammakia ◽  
Furat F. Afram ◽  
Kanad Ghose ◽  
Gamal Refai-Ahmed ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Heat Sink ◽  
Hot Spot ◽  
Three Dimensional ◽  
Memory Access ◽  
Microchannel Heat Sink ◽  
Multicore System ◽  
Floor Planning ◽  
Microchannel Cooling ◽  
Silicon Vias

The electronics industry is heading toward the three-dimensional (3D) microprocessor to cope with higher computing workloads. The 3D stacking of the processor and the memory components reduces the communication delay in multicore system-on-a-chip (SoCs), owing to reduced system size and shorter interconnects. The shorter interconnects in a multicore system lowers the memory access latencies and contributes to improvements in memory access bandwidth. The shorter interconnects in stacked architectures also enables small drivers for interconnections which further reduce interconnection-level-energy dissipations. On the down side, the 3D-stacked architectures have high thermal resistance, which in conjunction with poor thermal management techniques, poses a thermal threat to the reliability of the device. This paper establishes the significance of the microprocessor floor planning and single-phase microchannel cooling for solving the thermal issues arising in the 3D-stacked-quad-core processor. The 3D-stacked-quad-core processor considered in this study comprises of symmetric nonuniformly powered quad-core processor, liquid-cooled microchannel heat sink, dynamic random access memory (DRAM), thermal interface material (TIM), and heat spreader. The electrical through-silicon-vias (TSVs) between the processor and DRAM serve as interconnects, while the thermal TSVs reduce the internal thermal resistance. The effective cooling of the 3D-stacked-quad-core processor depends on the TSVs, quad-core layout and the optimized design of the microchannel heat sink for the desired coolant. The microchannel cooling of the 3D-stacked processor is done both by planar flow and impingement flow. The thermal efficiency of the cooling techniques is evaluated on the basis of hot spot temperature, hot spot spread, and number of hot spots.

Thermal Performance Analysis of Hybrid Jet Impingement/Microchannel Cooling for Concentrated Photovoltaic (CPV) Cells

2016 ◽  
Author(s):  
Afzal Husain ◽  
Mohd Ariz ◽  
Nasser A. Al-Azri ◽  
Nabeel Z. H. Al-Rawahi ◽  
Mohd. Z. Ansari
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Heat Sink ◽  
Three Dimensional ◽  
Jet Impingement ◽  
Constant Heat Flux ◽  
Pumping Power ◽  
High Concentration ◽  
Microchannel Cooling ◽  
Characteristic Relationship

The increase in the CPV temperature significantly reduces the efficiency of CPV system. To maintain the CPV temperature under a permissible limit and to utilize the unused heat from the CPVs, an efficient cooling and transportation of coolant is necessary in the system. The present study proposes a new design of hybrid jet impingements/microchannels heat sink with pillars for cooling densely packed PV cells under high concentration. A three-dimensional numerical model was constructed to investigate the thermal performance under steady state, incompressible and laminar flow. A constant heat flux was applied at the base of the substrate to imitate heated CPV surface. The effect of two dimensionless variables, i.e., ratios of standoff (distance from the nozzle exit to impingement surface) to jet diameter and jet pitch to jet diameter was investigated at several flow conditions. The performance of hybrid heat sink was investigated in terms of heat transfer coefficient, pressure-drop, overall thermal resistance and pumping power. The characteristic relationship between the overall thermal resistance and the pumping power was presented which showed an optimum design corresponding to S/Dj = 12 having lower overall thermal resistance and lower pumping power.

Single-Phase Microchannel Cooling for Stacked Single Core Chip and DRAM

2011 ◽  
Author(s):  
Anjali Chauhan ◽  
Bahgat Sammakia ◽  
Kanad Ghose ◽  
Gamal Refai-Ahmed ◽  
Dereje Agonafer
Keyword(s):  
Thermal Resistance ◽  
Thermal Management ◽  
Heat Sink ◽  
Single Phase ◽  
Cooling System ◽  
Three Dimensional ◽  
Form Factors ◽  
Memory Access ◽  
Thermal Interface Material ◽  
Level Energy

The stacking of processing and memory components in a three-dimensional (3D) configuration enables the implementation of processing systems with small form factors. Such stacking shortens the interconnection length between processing and memory components to dramatically lower the memory access latencies, and contributes to significant improvements in the memory access bandwidth. Both of these factors elevate overall system performance to levels that are not realizable with prevailing and other proposed solutions. The shorter interconnection lengths in stacked architectures also enable the use of smaller drivers for the interconnections, which in turn reduces interconnection-level energy dissipations. On the down side, stacking of processing and memory components introduces a significant thermal management challenge that is rooted in the high thermal resistance of stacked designs. This paper examines and evaluates three distinct solutions that address thermal management challenges in a system that stacks DRAM components onto a processing core. We primarily focus on three different configurations of a microchannel-based single-phase liquid cooling system with a traditional air-cooled heat sink. Our evaluations, which are intended to study the limits of each solution, assume a uniform power dissipation model for the processor and accounts for the thermal resistance offered by the thermal interface material (TIM), the interconnect layer, and through-silicon vias (TSVs). The liquid-cooled microchannel heat sink shows more promising results when integrated into the package than when added to the microprocessor package from outside.

Liquid Cooling of a Stacked Quad-Core Processor and DRAM Using Laminar Flow in Microchannels

2011 ◽  
Author(s):  
Anjali Chauhan ◽  
Bahgat Sammakia ◽  
Furat F. Afram ◽  
Kanad Ghose ◽  
Gamal Refai-Ahmed ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Heat Sink ◽  
Silicon Oxide ◽  
Hot Spot ◽  
Random Access ◽  
System Size ◽  
Thermal Interface Material ◽  
Liquid Cooling ◽  
Silicon Oxide Layer ◽  
Multicore System

Three dimensional (3D) stacking of the processor and memory components in high computing applications reduces the communication delay in multicore system-on-a-chip (SoCs) owing to reduced system size and shorter interconnects. The shorter interconnection length between the processing and memory components in a multicore system lowers the overall system access latencies and boosts the system performance. However, this 3D integration of the processors and memory exacerbates the reliability and thermal problems due to high thermal resistance of the stacked designs. Liquid cooling is the most promising solution to overcome this thermal problem arising in the 3D multicore systems. In this paper, we provide a 3D simulation model comprising of quad-core processor, dynamic random-access-memory (DRAM), liquid cooled microchannel heat sink and air-cooled heat sink. The thermal resistance offered by the silicon oxide layer and thermal interface material (TIM) has also been taken into account. The model assumes the integration of the thermal as well as electrical vias and considers the modified thermal conductivity of the materials in the stack. The cores of the quad-core processor are identical, have non-uniform power dissipation and are arranged in a symmetric layout. The quad-core layouts are based on the traditional and optimized floor plan of a single-core microprocessor. The paper reports the results for both planar flow and impingement flow in the microchannels. The thermal efficiency of the 3D design is evaluated on the basis of the hot spot temperature, hot spot spread and number of hot spots on the surface of the chip as well as DRAM.

Investigation of On-Chip Hot Spot Cooling Using Microchannel Heat Sink

2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang
Keyword(s):  
Heat Flux ◽  
Heat Sink ◽  
Hot Spots ◽  
Hot Spot ◽  
High Heat ◽  
High Heat Flux ◽  
Microchannel Heat Sink ◽  
Three Dimensional Model ◽  
Spot Cooling ◽  
On Chip

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.

THERMAL AND HYDRODYNAMIC PERFORMANCE OF A MICROCHANNEL HEAT SINK COOLED WITH CARBON NANOTUBES NANOFLUID

2016 ◽  
Vol 78 (10-2) ◽  
Author(s):  
Nik Ahmad Faiz Nik Mazlam ◽  
Normah Mohd-Ghazali ◽  
Thierry Mare ◽  
Patrice Estelle ◽  
Salma Halelfadl
Keyword(s):  
Thermal Resistance ◽  
Heat Sink ◽  
Operating Temperature ◽  
Heat Removal ◽  
Hydrodynamic Performance ◽  
Spherical Particles ◽  
Microchannel Heat Sink ◽  
Pumping Power ◽  
Rectangular Microchannel ◽  
Aspect Ratios

The microchannel heat sink (MCHS) has been established as an effective heat removal system in electronic chip packaging. With increasing power demand, research has advanced beyond the conventional coolants of air and water towards nanofluids with their enhanced heat transfer capabilities. This research had been carried out on the optimization of the thermal and hydrodynamic performance of a rectangular microchannel heat sink (MCHS) cooled with carbon nanotube (CNT) nanofluid, a coolant that has recently been discovered with improved thermal conductivity. Unlike the common nanofluids with spherical particles, nanotubes generally come in cylindrical structure characterized with different aspect ratios. A volume concentration of 0.1% of the CNT nanofluid is used here; the nanotubes have an average diameter and length of 9.2 nm and 1.5 mm respectively. The nanofluid has a density of 1800 kg/m3 with carbon purity 90% by weight having lignin as the surfactant. The approach used for the optimization process is based on the thermal resistance model and it is analyzed by using the non-dominated sorting multi-objective genetic algorithm. Optimized outcomes include the channel aspect ratio and the channel wall ratio at the optimal values of thermal resistance and pumping power. The optimized results show that, at high operating temperature of 40°C the use of CNT nanofluid reduces the total thermal resistance by 3% compared to at 20°C and consequently improve the thermal performance of the fluid. In terms of the hydrodynamic performance, the pumping power is also being reduced significantly by 35% at 40°C compared to the lower operating temperature.  

Microprocessor Silicon Die Temperature Prediction by Simplified Boundary Conditions

2015 ◽  
Author(s):  
Koji Nishi ◽  
Tomoyuki Hatakeyama ◽  
Shinji Nakagawa ◽  
Masaru Ishizuka
Keyword(s):  
Heat Transfer ◽  
Heat Conduction ◽  
Boundary Conditions ◽  
Thermal Resistance ◽  
Hot Spot ◽  
Three Dimensional ◽  
Thermal Design ◽  
Target Temperature ◽  
One Dimensional ◽  
Thermal Network

The thermal network method has a long history with thermal design of electronic equipment. In particular, a one-dimensional thermal network is useful to know the temperature and heat transfer rate along each heat transfer path. It also saves computation time and/or computation resources to obtain target temperature. However, unlike three-dimensional thermal simulation with fine pitch grids and a three-dimensional thermal network with sufficient numbers of nodes, a traditional one-dimensional thermal network cannot predict the temperature of a microprocessor silicon die hot spot with sufficient accuracy in a three-dimensional domain analysis. Therefore, this paper introduces a one-dimensional thermal network with average temperature nodes. Thermal resistance values need to be obtained to calculate target temperature in a thermal network. For this purpose, thermal resistance calculation methodology with simplified boundary conditions, which calculates thermal resistance values from an analytical solution, is also introduced in this paper. The effectiveness of the methodology is explored with a simple model of the microprocessor system. The calculated result by the methodology is compared to a three-dimensional heat conduction simulation result. It is found that the introduced technique matches the three-dimensional heat conduction simulation result well.

Thermal Optimization of a Microchannel Heat Sink With Trapezoidal Cross Section

2009 ◽  
Vol 131 (2) ◽  
Author(s):  
Afzal Husain ◽  
Kwang-Yong Kim
Keyword(s):  
Shape Optimization ◽  
Thermal Resistance ◽  
Objective Function ◽  
Response Surface ◽  
Heat Sink ◽  
Fractional Factorial ◽  
Surface Model ◽  
Microchannel Heat Sink ◽  
Reference Shape ◽  
Design Variables

A microchannel heat sink shape optimization has been performed using response surface approximation. Three design variables related to microchannel width, depth, and fin width are selected for optimization, and thermal resistance has been taken as objective function. Design points are chosen through a three-level fractional factorial design of sampling methods. Navier–Stokes and energy equations for steady, incompressible, and laminar flow and conjugate heat transfer are solved at these design points using a finite volume solver. Solutions are carefully validated with the analytical and experimental results and the values of objective function are calculated at the specified design points. Using the numerically evaluated objective-function values, a polynomial response surface model is constructed and the optimum point is searched by sequential quadratic programming. The process of shape optimization greatly improves the thermal performance of the microchannel heat sink by decreasing thermal resistance of about 12% of the reference shape. Sensitivity of objective function to design variables has been studied to utilize the substrate material efficiently.

Numerical Prediction of Thermal Performance of Water Cooled Multi-Stack Microchannel Heat Sink with Counterflow Arrangement

2011 ◽  
Vol 8 (1) ◽  
pp. 16-22 ◽  
Author(s):  
Pradeep Hegde ◽  
Mukesh Patil ◽  
K. N. Seetharamu
Keyword(s):  
Finite Element ◽  
Pressure Drop ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Heat Sink ◽  
Element Model ◽  
Channel Length ◽  
Computational Time ◽  
Microchannel Heat Sink ◽  
Method Performance

Thermal performance of a water cooled multistack microchannel heat sink with counterflow arrangement has been analyzed using the finite element method. Performance parameters such as thermal resistance, pressure drop, and pumping power are computed for a typical counterflow heat sink with different number of stacks. The temperature distribution in a typical multistack counterflow microchannel heat sink is obtained for different numbers of stacks and plotted along the channel length. A parametric study involving the effects of number of stacks and channel aspect ratio on thermal resistance and pressure drop of the heat sink is done. The finite element model developed for the analysis is simple and consumes less computational time.

Silicon Interposer Featuring Novel Electrical and Optical TSVs

2012 ◽  
Author(s):  
Paragkumar A. Thadesar ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Heat Sink ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
System Level ◽  
Performance Improvements ◽  
Fine Pitch ◽  
3D Integrated Circuits ◽  
Photonic Interconnects ◽  
Silicon Vias

Three-dimensional (3D) integrated circuits (ICs) yield system level performance improvements by providing high-bandwidth communication as well as opportunity for heterogeneous integration. It is envisioned that an area array of 3D stacked ICs can be interconnected using dense fine-pitch electrical and photonic interconnects on a silicon interposer. This paper presents a mechanically robust “thick” silicon interposer with novel electrical through-silicon vias (TSVs) and optical TSVs. The novel electrical TSVs described include polymer-clad TSVs and polymer-embedded vias. An advantage of using thick silicon interposer is that microchannels can be integrated in the thick silicon interposer to transfer a coolant to the 3D ICs with interlayer microfluidic heat sink or for the direct integration of a microfluidic heat-sink in the silicon interposer. However, as the thickness of silicon interposer increases, TSV electrical parasitics increase. Moreover, the coefficient of thermal expansion (CTE) mismatch between the copper TSV and silicon causes reliability issues. To reduce TSV capacitance as well as to reduce TSV stresses, polymer-clad electrical TSVs were fabricated. Using the same photodefinable polymer used for the cladding of electrical TSVs, optical TSVs were fabricated and characterized.

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