A Surface Energy Approach to Developing an Analytical Model for the Underfill Flow Process in Flip-Chip Packaging

2021 ◽  
Author(s):  
X.J. Yao ◽  
Weijie Jiang ◽  
Jiahui Yang ◽  
Junjie Fang ◽  
W.J. (Chris) Zhang
Keyword(s):  
Surface Energy ◽  
Analytical Model ◽  
Flip Chip ◽  
Cfd Simulation ◽  
Flow Front ◽  
New Approach ◽  
Solder Bumps ◽  
Regular Triangle ◽  
Filling Time ◽  
Flip Chip Packaging

Abstract This paper presents a new approach to formulating an analytical model for the underfill process in flip-chip packaging to predict the flow front and the filling time. The new approach is based on the concept of surface energy along with the energy conservation principle. This approach avoids the need of modeling the flow path to predict the flow front and the filling time and thus it is suitable to different configurations of solder bumps, including different shapes and arrangements of solder bumps in flip-chip packaging. An experiment along with the CFD simulation was performed based on a proprietarily developed testbed to verify the effectiveness of this approach. Both the experimental and simulation results show that the proposed approach along with its model is accurate for flip-chip packages with different configurations besides the configuration of a regular triangle arrangement of solder bumps and a spherical shape of the solder bump.

Surface Energy and Wettability Study of Flip Chip Packaging Materials

2011 ◽  
Vol 2011 (1) ◽  
pp. 000961-000970
Author(s):  
Jinlin Wang
Keyword(s):  
Surface Energy ◽  
Flip Chip ◽  
Substrate Surface ◽  
Solid Surfaces ◽  
Energy Calculation ◽  
Assembly Process ◽  
Flip Chip Packaging ◽  
Materials Used ◽  
Lead Free Solders ◽  
Ic Package

The surface energy of solid surfaces and surface tension of liquids are important parameters in the IC package assembly process. Wettability analyses have been completed for various materials used in the assembly process of flip chip packages, including underfills, substrates, fluxes, and lead free solders. We will highlight some of these results in this paper. We will focus our discussion on substrate surface energy analysis. A brief discussion of different surface energy methods and the liquid selection criteria will be given. The advantage and limitation of the surface energy calculation methods will be discussed. The data from several case studies will be presented. Our results show that contact angle and surface energy measurements are very useful for quality control and product development where interfacial properties are important.

A Model for Underfill Viscous Flow Considering the Resistance Induced by Solder Bumps

2004 ◽  
Vol 126 (2) ◽  
pp. 186-194 ◽  
Author(s):  
Chyi-Lang Lai ◽  
Wen-Bin Young
Keyword(s):  
Flip Chip ◽  
External Pressure ◽  
Good Prediction ◽  
Parallel Plates ◽  
Rectangular Array ◽  
Chip Technology ◽  
Solder Bumps ◽  
Proposed Model ◽  
Filling Time ◽  
Underfill Flow

During the underfill process, polymers driven by either capillary force or external pressure are filled at a low speed between the chip and substrate. Current methods treated the flow in the chip cavity as a laminar flow between parallel plates, which ignored the resistance induced by the solder bumps or other obstructions. In this study, the filling flow between solder bumps was simulated by a flow through a porous media. By using the superposition of flows through parallel plates and series of rectangular ducts, permeability of the underfill flow was fully characterized by the geometric arrangement of solder bumps and flat chips. The flow resistances caused by adjacent bumps were represented in its permeability. The model proposed in this study could provide a numerical approach to approximate and simulate the undefill process for flip-chip technology. Although the proposed model is applicable for any geometric arrangement of solder bumps, rectangular-array of solder bumps layout was used first for comparison with experimental results of other article. Comparisons of the flow-front shapes and filling time with the experimental data indicated that the flow simulation obtained from the proposed model gave a good prediction for the underfill flow.

A Theoretical Analysis of the Concept of Critical Clearance Toward a Design Methodology for the Flip-Chip Package

2007 ◽  
Vol 129 (4) ◽  
pp. 473-478 ◽  
Author(s):  
J. W. Wan ◽  
W. J. Zhang ◽  
D. J. Bergstrom
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Flow Characteristics ◽  
Quantitative Relation ◽  
Package Design ◽  
Solder Bumps ◽  
Filling Time ◽  
Encapsulation Process ◽  
Advanced Packaging ◽  
Gap Height

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon et al. (1999, “A Capillary-Driven Underfill Encapsulation Process,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

Underflow Process for Direct-Chip-Attachment Packaging

1998 ◽  
Vol 515 ◽  
Author(s):  
P. C. Li ◽  
G. L. Lehmann ◽  
J. Cascio ◽  
T. Driscoll ◽  
Y. J. Huang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Capillary Flow ◽  
Flow Behavior ◽  
Complex Function ◽  
Plane Channel ◽  
Flow Process ◽  
Wetting Properties ◽  
Solder Bumps ◽  
Flip Chip Packaging ◽  
Measured Flow

ABSTRACTIn flip-chip packaging an underfill mixture is placed into the chip-to-substrate standoff created by the array of solder bumps, using a capillary flow process. The flow behavior is a complex function of the mixture properties, the wetting properties, and the flow geometry. This paper reports on the use of a plane channel capillary flow to characterize underfill materials. The measured flow behavior provides evidence that both the contact angle (θ) and the suspension viscosity (μapp) vary with time under the Influence of changing flow conditions. This nonlinear fluid behavior is modeled for the flow of both model suspensions and commercial underfill materials using an extended Washburn model.

Surface energetic-based analytical filling time model for flip-chip underfill process

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Fei Chong Ng ◽  
Mohamad Aizat Abas
Keyword(s):  
Analytical Model ◽  
Flip Chip ◽  
Current Model ◽  
Analytical Models ◽  
Time Model ◽  
Content Type ◽  
Package Design ◽  
The Past ◽  
Filling Time ◽  
Underfill Flow

Purpose This paper aims to present new analytical model for the filling times prediction in flip-chip underfill encapsulation process that is based on the surface energetic for post-bump flow. Design/methodology/approach The current model was formulated based on the modified regional segregation approach that consists of bump and post-bump regions. Both the expansion flow and the subsequent bumpless flow as integrated in the post-bump region were modelled considering the surface energy–work balance. Findings Upon validated with the past underfill experiment, the current model has the lowest root mean square deviation of 4.94 s and maximum individual deviation of 26.07%, upon compared to the six other past analytical models. Additionally, the current analytically predicted flow isolines at post-bump region are in line with the experimental observation. Furthermore, the current analytical filling times in post-bump region are in better consensus with the experimental times as compared to the previous model. Therefore, this model is regarded as an improvised version of the past filling time models. Practical implications The proposed analytical model enables the filling time determination for flip-chip underfill process at higher accuracy, while providing more precise and realistic post-bump flow visualization. This model could benefit the future underfill process enhancement and package design optimization works, to resolve the productivity issue of prolonged filling process. Originality/value The analytical underfill studies are scarce, with only seven independent analytical filling time models being developed to date. In particular, the expansion flow of detachment jump was being considered in only two previous works. Nonetheless, to the best of the authors’ knowledge, there is no analytical model that considered the surface energies during the underfill flow or based on its energy–work balance. Instead, the previous modelling on post-bump flow was based on either kinematic or geometrical that is coupled with major assumptions.

A Further Study on the Analytical Model for the Permeability in Flip-Chip Packaging

2018 ◽  
Vol 140 (1) ◽  
Author(s):  
X. J. Yao ◽  
J. J. Fang ◽  
Wenjun Zhang
Keyword(s):  
Porous Medium ◽  
Analytical Model ◽  
Flip Chip ◽  
Flow Behavior ◽  
Cross Sectional Area ◽  
Sectional Area ◽  
Cross Sectional ◽  
Proposed Model ◽  
Flip Chip Packaging ◽  
Pore Permeability

The notion of permeability is very important in understanding and modeling the flow behavior of fluids in a special type of porous medium (i.e., the underfill flow in flip-chip packaging). This paper presents a new concept regarding permeability in a porous medium, namely two types of permeability: superficial permeability (with consideration of both the pore cross-sectional area and the solid matrix cross-sectional area) and pore permeability (with consideration of the pore cross-sectional area only). Subsequently, the paper proposes an analytical model (i.e., equation) for the pore permeability and superficial permeability of an underfill porous medium in a flip-chip packaging, respectively. The proposed model along with several similar models in literature is compared with a reliable numerical model developed with the computational fluid dynamics (CFD) technique, and the result of the comparison shows that the proposed model for permeability is the most accurate one among all the analytical models in literature. The main contributions of the paper are as follows: (1) the provision of a more accurate analytical model for the permeability of an underfill porous medium in flip-chip packaging, (2) the finding of two types of permeability depending on how the cross-sectional area is taken, and (3) the correction of an error in the others' model in literature.

Underfill Injection Molding in Flip-Chip Packaging with Different Bumps Array Arrangements

2008 ◽  
Vol 594 ◽  
pp. 163-168
Author(s):  
Chao Ming Lin ◽  
Chun Yi Chu ◽  
Wei Lin Chang
Keyword(s):  
Injection Molding ◽  
Thin Shell ◽  
Flip Chip ◽  
Shear Strain Rate ◽  
Flow Front ◽  
Injection Process ◽  
Packing Pressure ◽  
Ic Packaging ◽  
Flip Chip Packaging ◽  
Cavity Filling

The injection molding IC packaging process involves chip packaging and encapsulation techniques comprising mainly of cavity-filling and curing processes. In this paper, the complex 3D geometries and flow behaviors are simplified and modeled by a 2.5D thin-shell simulation. Important aspects of the cavity-filling process include the choosing of bumps array types, the cavity geometry, the injection process, the packing pressure, and the process temperature. The current investigation considers the filling and curing in the different bumps array types. It is shown that the applicable array arrangement provides improved filling results on the flow front, curing, shear strain-rate and velocity vector distributions. These results show the better choice using the geometry parameters in the bumps array arrangement is to consider the performances of the local and global penetrations together.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Sign in / Sign up

Export Citation Format

Share Document