Thermal Performance Evaluation of New Power QFN (Quad Flat No Lead) Packages for Automotive Applications

2004 ◽  
Author(s):  
Victor Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Steady State ◽  
Thermal Performance ◽  
Numerical Study ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Automotive Applications ◽  
Isothermal Boundary ◽  
Die Attach ◽  
Transient Thermal ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the novel Power Quad Flat No Lead (PQFN) packages for automotive applications. Several PQFN packages are investigated, ranging from smaller die/flag size to larger ones, single or multiple heat sources, operating under various powering and boundary conditions. The steady state and transient thermal performance are compared to those of the classical packages, and the impact of the thicker lead frame and die attach material on the overall thermal behavior is also evaluated. Under one steady state (1W) operating scenario, the PQFN package reaches a peak temperature of ~106.3°C, while under 37W@40ms of transient powering, the peak temperature reached by the corner FET is ~260.8°C. With an isothermal boundary (85°C) attached to the board backside, the junction temperature does not change, as the PCB has no significant thermal impact. However, when the isothermal boundary is attached to package bottom, it leads to a drop in by almost 20% after 40 ms. Additional transient cases are evaluated, with an emphasis on the superior thermal performance of this new class of power packages for automotive applications.

Steady-State and Transient Thermal Performance Optimization of Power Automotive Modules

2009 ◽  
Author(s):  
Victor Chiriac
Keyword(s):  
Steady State ◽  
Thermal Performance ◽  
Numerical Study ◽  
Peak Temperature ◽  
System Level ◽  
Main Concern ◽  
Thermal Impact ◽  
Automotive Applications ◽  
Isothermal Boundary ◽  
Transient Thermal

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of power packages for automotive applications. The automotive industry deals on a daily basis with various package and module-level thermal issues when managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of IC incorporation into a system module, for present and future product development. Several packages are investigated, ranging from smaller die/flag size to larger ones, single or multiple heat sources, operating under various powering and boundary conditions. The steady state and transient thermal impact of the thicker lead frame and die attach material on the overall thermal behavior is evaluated. The main concern is exceeding the thermal budget at an external ambient temperature of 85°C, specific for the relatively extreme automotive operating environments. Under one steady state (1W) operating scenario, the PQFN package reaches a peak temperature of ∼106.3°C, while under 37W@40ms of transient powering, the peak temperature reached by the corner FET is ∼260.8°C. With an isothermal boundary (85°C) attached to the board backside, the junction temperature does not change, as the PCB has no significant thermal impact. When the isothermal boundary is attached to package bottom, peak temperature drops by 20% after 40 ms. Additional system level with multiple optimized packages placed on a custom PCB is evaluated numerically and experimentally, placing an emphasis on the superior thermal performance of this new class of power packages for automotive applications. The optimized numerical model approximates closely the empirical results (121–126°C vs. 127.5°C), within 1–2%.

System Level Thermal Performance Evaluation of New Inverted Exposed Pad Packages for Automotive Applications

2006 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Peak Temperature ◽  
System Level ◽  
Total Power ◽  
Automotive Applications ◽  
Typical Application ◽  
Cu Alloy ◽  
Die Attach ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the novel 54 lead SOIC (with inverted exposed Cu pad) packages for automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rjhs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, a comparison with a different exposed pad package is made. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package. Several cases are evaluated in the paper, with an emphasis on the superior thermal performance of new packages for automotive applications.

Thermal Performance Optimization of Radio Frequency Packages for Wireless Communication

2004 ◽  
Vol 126 (4) ◽  
pp. 429-434 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
Vern Hause
Keyword(s):  
Wireless Communication ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Metal Layer ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, either at the module level or at the system (module-board stack-up) level. The wireless communication industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A three-dimensional conjugate numerical study was conducted to evaluate the thermal performance of gallium arsenic die packaged in quad flat no-lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: (1) one for standard operating parameters and (2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3×3 mm QFN under normal powering conditions is ∼138.5 °C (or 119 °C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ∼186 °C (or 125 °C/W junction-to-air thermal resistance). In both cases, the top Au metal layer has a limited impact on lateral heat spreading. Under extreme powering conditions, the 5×5 mm PQFN package reaches a peak temperature of ∼126 °C (66 °C/W thermal resistance). A ∼32% reduction in peak temperature is achieved with the 5×5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe, and additional board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package will lead to only 3% reduction in peak temperature. By comparison, for both packages, the die attach material (conductive epoxy versus solder) will have a significant impact on the overall reduction in peak temperature (∼12%). Experimental measurements using an infrared microscope are performed to validate the numerical results. The results indicate good agreement (∼6% discrepancy) between the numerical model and the measurement.

Thermal Performance Optimization of RF Packages for Wireless Communication

2003 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
Vern Hause
Keyword(s):  
Wireless Communication ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Metal Layer ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, either at the module level or at the system (module-board stack-up) level. The wireless communication industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a new family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A 3-D conjugate numerical study was conducted to evaluate the thermal performance of Gallium Arsenic (GaAs) die packaged in Quad Flat No Lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a Power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: 1) one for standard operating parameters and 2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3×3 mm QFN under normal powering conditions is ∼138.5°C (or 119°C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ∼186°C (or 125°C/W junction-to-air thermal resistance). In both cases, the top Au metal layer has a limited impact on lateral heat spreading. Under extreme powering conditions, the 5×5 mm PQFN package reaches a peak temperature of ∼126°C (66°C/W thermal resistance). A ∼32% reduction in peak temperature is achieved with the 5×5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe and more board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package will lead to only 3% reduction in peak temperature. By comparison, for both packages, the die attach material (conductive epoxy vs. solder) will have a significant impact on the overall reduction in peak temperature (∼12%). Experimental measurements using an Infrared (IR) Microscope are performed to validate the numerical results. The results indicate good agreement (∼6% discrepancy) between the numerical model and the measurement.

Thermal Assessment of Cooling System Incorporating Heat Sink and Embedded Heat Pipes for Testing High Power Microelectronics

2005 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Steady State ◽  
Heat Pipe ◽  
Thermal Performance ◽  
Heat Sink ◽  
Heat Pipes ◽  
Optimal Operation ◽  
Operating Conditions ◽  
Peak Temperature ◽  
Testing System ◽  
The Impact

A numerical study was conducted to model the transient thermal behavior of a complex testing system including multiple fans, a mixing enclosure, copper inserts and a leaded package dissipating large amounts of power over short time durations. The system is optimized by choosing appropriate heat sink/fan structure for the efficient operation of the device under constant powering. The intent of the study is to provide a better understanding and prediction of a transient powering scenario at high powering levels, while evaluating the impact of alternative cooling fan/heat pipe designs on the thermal performance of the testing system. One design is chosen due to its effective thermal performance and assembly simplicity, with the package embedded in heat sink base with multiple (5) heat pipes. The peak temperature reached by the modified design with 4 cooling fans is ~95°C, with the corresponding Rja thermal resistance ~0.58°C/W. For the transient study (with embedded heat pipes and 4 fans), after one cycle, both peak temperature (at 45 s) and the end temperature (at 49 s) decrease as compared to the previous no heat pipe/single fan case (the end temperature reduces by ~16%). The temperature drop between peak and end for each cycle is ~80.2°C, while the average power per transient cycle is ~31.27W. With this power, the design with 5 perpendicular heat pipes, 4 fans and insert reaches a steady state peak temperature of ~98°C. Applying the superposition principle to the steady state value and 40.1°C fluctuation, the maximum transient temperature after a large number of cycles will not exceed ~138.1°C, satisfying the thermal budget under the current operating conditions. The benefit of the study is related to the possibility to extract the maximum and minimum temperatures for a real test involving a large number of heating-cooling cycles, yet maintaining the initial and peak temperatures within a certain range for the optimal operation of the device. The flow and heat transfer fields are investigated; using a combination of numerical and analytical methods, the thermal performance of the device undergoing large number of periodic thermal cycles is predicted. The comparison between measurement and simulation shows good agreement.

Impact of Die Attach Material and Substrate Design on RF GaAs Power Amplifier Devices Thermal Performance

2003 ◽  
Vol 125 (4) ◽  
pp. 589-596 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Conductivity ◽  
Layer Thickness ◽  
Power Amplifier ◽  
Thermal Performance ◽  
Metal Layer ◽  
Low Cost ◽  
Organic Substrate ◽  
Junction Temperature ◽  
Die Attach ◽  
The Impact

The latest commercial applications for microelectronics use GaAs material for RF power amplifier (PA) devices. This leads to the necessity of identifying low cost packaging solutions with high standards for reliability, electrical, and thermal performance. A detailed thermal analysis for the wirebonded GaAs devices is performed using numerical simulations. The main interest of the study focuses on the impact of die attach thermal conductivity (1.0–50.0 W/mK), substrate’s top metal layer thickness (25–50 μm), and via wall thickness (25–50 μm) on GaAs IC device overall thermal performance. The study uses a two-layer organic substrate. The peak temperatures reached by the PA stages range from 99.6°C to 120.3°C, below the prohibitive/critical value of 150°C (based on 85°C ambient temperature). The increase of die attach thermal conductivity from 1.0 to 7.0 W/mK led to a decrease in peak temperatures of up to 18°C, with larger decay between 1 and 2.4 W/mK. The largest temperature differences were obtained by varying the thermal via thickness, as opposed to only increasing the top metal layer thickness. The peak temperatures and corresponding junction-to-ambient thermal resistances are thoroughly documented. With the same die attach thickness, for a thermal conductivity much larger than 7 W/mK, the impact on the PA’s peak temperature is insignificant. The die attach solder material (with a large thermal conductivity) leads to only a small (2.5°C) decrease in the PA junction temperature.

System Level Thermal Performance Evaluation of Inverted Exposed Pad Packages

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001635-001655
Author(s):  
Victor Chiriac
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Peak Temperature ◽  
System Level ◽  
Total Power ◽  
Worst Case ◽  
Typical Application ◽  
Cu Alloy ◽  
Die Attach ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the 54 lead SOIC (with inverted exposed Cu pad) packages for advanced automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rj-hs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, compared different exposed pad packages. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package.

Optimal Thermal Management of Microelectronic Packages

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001617-001634
Author(s):  
Victor Chiriac
Keyword(s):  
Thermal Resistance ◽  
Numerical Study ◽  
Metal Layer ◽  
Cost Effective ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach ◽  
System Module ◽  
Multiple Challenges

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, at module and at system (module-board stack-up) levels. The microelectronics industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A 3-D conjugate numerical study was conducted to evaluate the thermal performance of Gallium Arsenic (GaAs) die packaged in Quad Flat No Lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a Power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: 1) one for standard operating parameters and 2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3x3 mm QFN under normal powering conditions is ~138.5°C (or 119°C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ~186°C (or 125°C/W junction-to-air thermal resistance). The top Au metal layer has limited impact on lateral heat spreading. Under extreme powering conditions, the PQFN package reaches a peak temperature of ~126°C (66°C/W thermal resistance). A ~32% reduction in peak temperature is achieved with the 5x5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe and more board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package leads to only 3% reduction in peak temperature. By comparison, the die attach material (conductive epoxy vs. solder) has significant impact on overall reduction in peak temperature (~12%). Experimental measurements using Infrared (IR) Microscope are performed to validate the numerical results.

An Investigation of the Effect of interrupted fin arrangements on the Thermal Performance of a Heat Sink under a Free Convection Condition

2019 ◽  
Vol 7 (1) ◽  
pp. 43-53
Author(s):  
Abbas Jassem Jubear ◽  
Ali Hameed Abd
Keyword(s):  
Heat Transfer ◽  
Steady State ◽  
Natural Convection ◽  
Thermal Performance ◽  
Heat Sink ◽  
Numerical Study ◽  
Ansys Fluent ◽  
Fluent Software ◽  
Steady State Heat ◽  
Steady State Heat Transfer

The heat sink with vertically rectangular interrupted fins was investigated numerically in a natural convection field, with steady-state heat transfer. A numerical study has been conducted using ANSYS Fluent software (R16.1) in order to develop a 3-D numerical model.  The dimensions of the fins are (305 mm length, 100 mm width, 17 mm height, and 9.5 mm space between fins. The number of fins used on the surface is eight. In this study, the heat input was used as follows: 20, 40, 60, 80, 100, and 120 watts. This study focused on interrupted rectangular fins with a different arrangement and angle of the fins. Results show that the addition of interruption in fins in various arrangements will improve the thermal performance of the heat sink, and through the results, a better interruption rate as an equation can be obtained.

Modeling Strategy in Evaluating Thermal Performance of an RF Module for Wireless Communications

2004 ◽  
Author(s):  
Victor Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Performance ◽  
Thermal Characteristics ◽  
Simulation Models ◽  
Operating Conditions ◽  
Peak Temperature ◽  
Load Cells ◽  
Die Temperature ◽  
Rf Module ◽  
Modeling Strategy ◽  
The Impact

A detailed study was performed to evaluate the thermal performance of RF Modules and to identify meaningful correlations between specific design characteristics and the power dissipation needed to satisfy the required thermal budget under various critical operating conditions. The investigation focuses on the thermal characteristics of the RF module die layout and transistor cells, and on the thermal impact of the metallic air bridges connecting the load cells to the collector pads/vias to the overall thermal performance of the RF module. A first-pass modeling predicts higher temperatures than IR measurement, by ~20–30%. The addition of the die layout air bridges connecting the load cells in the detailed simulation models leads to a predicted air bridge temperature of ~9% higher than the IR measurement. Additional modeling reveals that between the open (not encapsulated) and the closed module, the die peak temperature differs by less than 3 °C, most of the heat being dissipated through the substrate and board to the heat stage. Thus, the impact of mold compound is insignificant. For a closed module, the mold compound helps dissipate the heat, so the die temperature is slightly cooler than for the open module (<<3°C). This suggests that the die peak temperature measured in an open module can be adjusted (by subtracting 2–3°C) to represent the die temperature in a closed module.

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