Impact of Die Attach Material and Substrate Design on RF GaAs Power Amplifier Devices Thermal Performance

2003 ◽  
Vol 125 (4) ◽  
pp. 589-596 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Conductivity ◽  
Layer Thickness ◽  
Power Amplifier ◽  
Thermal Performance ◽  
Metal Layer ◽  
Low Cost ◽  
Organic Substrate ◽  
Junction Temperature ◽  
Die Attach ◽  
The Impact

The latest commercial applications for microelectronics use GaAs material for RF power amplifier (PA) devices. This leads to the necessity of identifying low cost packaging solutions with high standards for reliability, electrical, and thermal performance. A detailed thermal analysis for the wirebonded GaAs devices is performed using numerical simulations. The main interest of the study focuses on the impact of die attach thermal conductivity (1.0–50.0 W/mK), substrate’s top metal layer thickness (25–50 μm), and via wall thickness (25–50 μm) on GaAs IC device overall thermal performance. The study uses a two-layer organic substrate. The peak temperatures reached by the PA stages range from 99.6°C to 120.3°C, below the prohibitive/critical value of 150°C (based on 85°C ambient temperature). The increase of die attach thermal conductivity from 1.0 to 7.0 W/mK led to a decrease in peak temperatures of up to 18°C, with larger decay between 1 and 2.4 W/mK. The largest temperature differences were obtained by varying the thermal via thickness, as opposed to only increasing the top metal layer thickness. The peak temperatures and corresponding junction-to-ambient thermal resistances are thoroughly documented. With the same die attach thickness, for a thermal conductivity much larger than 7 W/mK, the impact on the PA’s peak temperature is insignificant. The die attach solder material (with a large thermal conductivity) leads to only a small (2.5°C) decrease in the PA junction temperature.

Impact of Die Attach Material and Substrate Design on RF GaAs Power Amplifier Devices Thermal Performance

2001 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien -Yu Tom Lee
Keyword(s):  
Thermal Conductivity ◽  
Layer Thickness ◽  
Power Amplifier ◽  
Thermal Performance ◽  
Metal Layer ◽  
Low Cost ◽  
Organic Substrate ◽  
Die Attach ◽  
Commercial Applications ◽  
The Impact

Abstract The latest commercial applications for microelectronics use GaAs material for RF Power Amplifier devices. This leads to the necessity of identifying low cost packaging solutions with high standards for reliability, electrical and thermal performance. A detailed thermal analysis for the wirebonded GaAs devices is performed using numerical simulations. The main interest of the study focuses on the impact of die attach thermal conductivity (1.0 to 7.0 W/mK), substrate’s top metal layer thickness (25 to 50 μm), and via wall thickness (25 to 50 μm) on GaAs IC device overall thermal performance. The study uses a 2-layer organic substrate; the die attach thickness is 15μm. The peak temperatures reached by PA stages range from 102.7°C to 113.5°C, below the prohibitive/critical value of 150°C (based on 85°C ambient temperature). The increase of die attach thermal conductivity (3 times) led to a slight decrease in peak temperatures (up to 5°C) and the decay is much larger between the cases with 1 and 2.4 W/mK. The largest temperature differences were obtained by varying the thermal via thickness, as opposed to only increasing the top metal layer thickness. The peak temperatures and corresponding junction to ambient thermal resistances are documented. It is determined that for the same die attach thickness, for a thermal conductivity larger than 7 W/mK, the impact on the PA’s peak temperature is insignificant.

Thermal Performance Optimization of Radio Frequency Packages for Wireless Communication

2004 ◽  
Vol 126 (4) ◽  
pp. 429-434 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
Vern Hause
Keyword(s):  
Wireless Communication ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Metal Layer ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, either at the module level or at the system (module-board stack-up) level. The wireless communication industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A three-dimensional conjugate numerical study was conducted to evaluate the thermal performance of gallium arsenic die packaged in quad flat no-lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: (1) one for standard operating parameters and (2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3×3 mm QFN under normal powering conditions is ∼138.5 °C (or 119 °C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ∼186 °C (or 125 °C/W junction-to-air thermal resistance). In both cases, the top Au metal layer has a limited impact on lateral heat spreading. Under extreme powering conditions, the 5×5 mm PQFN package reaches a peak temperature of ∼126 °C (66 °C/W thermal resistance). A ∼32% reduction in peak temperature is achieved with the 5×5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe, and additional board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package will lead to only 3% reduction in peak temperature. By comparison, for both packages, the die attach material (conductive epoxy versus solder) will have a significant impact on the overall reduction in peak temperature (∼12%). Experimental measurements using an infrared microscope are performed to validate the numerical results. The results indicate good agreement (∼6% discrepancy) between the numerical model and the measurement.

An Assessment of the Impact of Interconnect Strategies on Thermal Performance of GaAs Power Amplifier IC Devices

2001 ◽  
Author(s):  
V. H. Adams ◽  
T.-Y. Tom Lee
Keyword(s):  
Thermal Resistance ◽  
Power Amplifier ◽  
Thermal Performance ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Wire Bond ◽  
Die Attach ◽  
The Impact

Abstract Alternative interconnect strategies are being considered in place of the standard wire bond interconnect for GaAs power amplifier MMIC devices due to cost and electrical performance improvements. The package/die thermal performance consequences are potentially high-risk issue to these interconnect strategies and requires evaluation. Thermal simulations are conducted to compare and evaluate the thermal performances of three interconnect strategies: wire bond, gold post-flip chip, and through via interconnects. The test vehicle simulated is a three-stage, dual band power amplifier integrated circuit dissipating approximately 5 W steady-state power. Parametric studies are conducted to evaluate the impact of the printed circuit board, die thickness, solid gold vias, and design enhancements on package thermal performance. Best thermal performance is provided by a wire bonded, thin GaAs die attached with solder die attach to a printed circuit board that maximizes the number of plated-through-holes directly under the die. This configuration results in a best case junction-to-heat sink thermal resistance of 12 °C/W. Optimum flip chip and through via designs result in degraded thermal performance compared to the above described wire bond design but may have acceptable thermal performance. For these simulations, predicted junction-to-heatsink thermal resistance is in a range of 15–20 °C/W and is better than a comparable wire bonded design that uses a conductive epoxy die attach material.

Thermal Performance Optimization of RF Packages for Wireless Communication

2003 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
Vern Hause
Keyword(s):  
Wireless Communication ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Metal Layer ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, either at the module level or at the system (module-board stack-up) level. The wireless communication industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a new family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A 3-D conjugate numerical study was conducted to evaluate the thermal performance of Gallium Arsenic (GaAs) die packaged in Quad Flat No Lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a Power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: 1) one for standard operating parameters and 2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3×3 mm QFN under normal powering conditions is ∼138.5°C (or 119°C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ∼186°C (or 125°C/W junction-to-air thermal resistance). In both cases, the top Au metal layer has a limited impact on lateral heat spreading. Under extreme powering conditions, the 5×5 mm PQFN package reaches a peak temperature of ∼126°C (66°C/W thermal resistance). A ∼32% reduction in peak temperature is achieved with the 5×5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe and more board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package will lead to only 3% reduction in peak temperature. By comparison, for both packages, the die attach material (conductive epoxy vs. solder) will have a significant impact on the overall reduction in peak temperature (∼12%). Experimental measurements using an Infrared (IR) Microscope are performed to validate the numerical results. The results indicate good agreement (∼6% discrepancy) between the numerical model and the measurement.

Thermal Performance Evaluation of New Power QFN (Quad Flat No Lead) Packages for Automotive Applications

2004 ◽  
Author(s):  
Victor Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Steady State ◽  
Thermal Performance ◽  
Numerical Study ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Automotive Applications ◽  
Isothermal Boundary ◽  
Die Attach ◽  
Transient Thermal ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the novel Power Quad Flat No Lead (PQFN) packages for automotive applications. Several PQFN packages are investigated, ranging from smaller die/flag size to larger ones, single or multiple heat sources, operating under various powering and boundary conditions. The steady state and transient thermal performance are compared to those of the classical packages, and the impact of the thicker lead frame and die attach material on the overall thermal behavior is also evaluated. Under one steady state (1W) operating scenario, the PQFN package reaches a peak temperature of ~106.3°C, while under 37W@40ms of transient powering, the peak temperature reached by the corner FET is ~260.8°C. With an isothermal boundary (85°C) attached to the board backside, the junction temperature does not change, as the PCB has no significant thermal impact. However, when the isothermal boundary is attached to package bottom, it leads to a drop in by almost 20% after 40 ms. Additional transient cases are evaluated, with an emphasis on the superior thermal performance of this new class of power packages for automotive applications.

Understanding Mold Compound Behavior on Flip Chip QFN Packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000125-000128
Author(s):  
Ruby Ann M. Camenforte ◽  
Jason Colte ◽  
Richard Sumalinog ◽  
Sylvester Sanchez ◽  
Jaimal Williamson
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Gelation Time ◽  
Molding Process ◽  
Design Quality ◽  
Low Resistance ◽  
Die Attach

Abstract Overmolded Flip Chip Quad Flat No-lead (FCQFN) is a low cost flip chip on leadframe package where there is no need for underfill, and is compatible with Pb free or high Pb metallurgy. A robust leadframe design, quality solder joint formation and an excellent molding process are three factors needed to assemble a high performance FCQFN. It combines the best of both wirebonded QFN and wafer chip scale devices. For example, wafer chip scale has low resistance, but inadequate thermal performance (due to absence of thermal pad), whereas wirebonded QFN has good thermal performance (i.e., heat dissipated through conductive die attach material, through the pad and to the board) but higher resistance. Flip chip QFN combines both positive aspects – that is: low resistance and good thermals. One of the common defects for molded packages across the semiconductor industry is the occurrence of mold voiding as this can potentially affect the performance of a device. This paper will discuss how mold voiding is mitigated by understanding the mold compound behavior on flip chip QFN packages. Taking for example the turbulent mold flow observed on flip chip QFN causing mold voids. Mold compound material itself has a great contribution to mold voids, hence defining the correct attributes of the mold compound is critical. Altering the mold compound property to decrease the mold compound rheology is a key factor. This dynamic interaction between mold compound and flip chip QFN package configuration is the basis for a series of design of experiments using a full factorial matrix. Key investigation points are establishing balance in mold compound chemistry allowing flow between bump pitch, as well as the mold compound rheology, where gelation time has to be properly computed to allow flow across the leadframe. Understanding the flow-ability of mold compound for FCQFN, the speed of flow was optimized to check on its impact on mold voids. Mold airflow optimization is also needed to help fill in tighter bump spacing but vacuum-on time needs to be optimized as well.

Thermo-Optic Tuning Efficiency of Micro Ring Resonators on Low Thermal Resistance Silicon Photonics Substrates

2017 ◽  
Author(s):  
Shenghui Lei ◽  
Alexandre Shen ◽  
Ryan Enright
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Silicon Photonics ◽  
Communication Systems ◽  
Device Fabrication ◽  
Ring Resonators ◽  
Wide Range ◽  
Soi Substrates ◽  
The Impact

Silicon photonics has emerged as a scalable technology platform for future optotelectronic communication systems. However, the current use of SiO2-based silicon-on-insulator (SOI) substrates presents a thermal challenge to integrated active photonic components such as lasers and semiconductor optical amplifiers due to the poor thermal properties of the buried SiO2 optical cladding layer beneath these devices. To improve the thermal performance of these devices, it has been suggested that SiO2 be replaced with aluminum nitride (AlN); a dielectric with suitable optical properties to function as an effective optical cladding that, in its crystalline state, demonstrates a high thermal conductivity (∼100× larger than SiO2 in current SOI substrates). On the other hand, the tuning efficiencies of thermally-controlled optical resonators and phase adjusters, crucial components for widely tunable lasers and modulators, are directly proportional to the thermal resistance of these devices. Therefore, the low thermal conductivity buried SiO2 layer in the SOI substrate is beneficial. Moreover, to further improve the thermal performance of these devices air trenches have been used to further thermally isolate these devices, resulting in up to ∼10× increase in tuning efficiency. Here, we model the impact of changing the buried insulator on a SOI substrate from SiO2 to high quality AlN on the thermal performance of a MRR. We map out the thermal performance of the MRR over a wide range of under-etch levels using a thermo-electrical model that incorporates a pseudo-etching approach. The pseudo-etching model is based on the diffusion equation and distinguishes the regions where substrate material is removed during device fabrication. The simulations reveal the extent to which air trenches defined by a simple etch pattern around the MRR device can increase the thermal resistance of the device. We find a critical under-etch below which no benefit is found in terms of the MRR tuning efficiency. Above this critical under-etch, the tuning efficiency increases exponentially. For the SiO2-based MRR, the thermal resistance increases by ∼7.7× between the un-etched state up to the most extreme etch state. In the unetched state, the thermal resistance of the AlN-based MRR is only ∼4% of the SiO2-based MRR. At the extreme level of under-etch, the thermal resistance of the AlN-based MRR is still only ∼60% of the un-etched SiO2-based MRR. Our results suggest the need for a more complex MRR thermal isolation strategy to significantly improve tuning efficiencies if an AlN-based SOI substrate is used.

System Level Thermal Performance Evaluation of New Inverted Exposed Pad Packages for Automotive Applications

2006 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Peak Temperature ◽  
System Level ◽  
Total Power ◽  
Automotive Applications ◽  
Typical Application ◽  
Cu Alloy ◽  
Die Attach ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the novel 54 lead SOIC (with inverted exposed Cu pad) packages for automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rjhs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, a comparison with a different exposed pad package is made. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package. Several cases are evaluated in the paper, with an emphasis on the superior thermal performance of new packages for automotive applications.

COMPARISON OF FOWLP VS QFN PACKAGE FROM THERMAL ASPECT

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000248-000271 ◽  
Author(s):  
Qun Wan
Keyword(s):  
Thermal Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Wafer Level ◽  
Element Analysis ◽  
Rf Power Amplifier ◽  
Thermal Test ◽  
Die Attach ◽  
Bottleneck Identification ◽  
Resistance Breakdown

The QFN package dominates IC industry with a small number of IOs due to its simplicity, maturity and low cost in mass production. However, as the industry progresses toward portability and smaller size, thinner and more compact packages such as Fan Out Wafer Level Package (FOWLP) is a better option/solution than QFN package. Due to its flip chip configuration, imbedded redistribution (RDL) interconnection and elimination of die attach layer, the FOWLP package has potential to surpass QFN package in thermal performance. This paper utilized a typical 3-stage RF power amplifier die as a thermal test vehicle, packaged with FOWLP and QFN, built FEA (Finite Element Analysis) thermal models and analyzed the thermal performance by thermal resistance breakdown and thermal bottleneck identification. Comparison of FOWLP and QFN shows that the heat paths and bottlenecks within each package are quite different. In QFN package, bottleneck lies in the die attach layer while in FOWLP package, it lies in the backend layers on the die and the RDL vias. FOWLP package may also require better thermal vias performance in PCB due to smaller footprint of LGA/Solder. Large horizontal heat spreading in a poorly design PCB may offset the thermal advantages in FOWLP package. The simulation results of both packages have good correlation with Infrared (IR) measurement of corresponding thermal test vehicles.

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