Printed Circuit Board Pad Crater Test Methods and Sample Design

2012 ◽  
Author(s):  
Todd Embree ◽  
Deassy Novita ◽  
Gary Long ◽  
Satish Parupalli
Keyword(s):  
Test Data ◽  
Printed Circuit Board ◽  
Test Methods ◽  
Circuit Board ◽  
Lead Free ◽  
Sample Design ◽  
Printed Circuit ◽  
Highly Sensitive ◽  
Halogen Free ◽  
Lead Free Solders

The continual drive toward smaller second level interconnect dimensions, along with the introduction of Halogen-Free circuit board materials and increased process temperatures of Lead-Free solders, have all contributed to a more frequent occurrence of Pad Crater damage in circuit board materials during manufacturing and test processes. This paper addresses the methodology and test data of some common industry methods used to evaluate Pad Crater strength in circuit board materials. Pad Crater test data is highly sensitive to sample design; as a result a discussion of sample design criteria is also included.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

Site Redressing Techniques and Rework of Lead-Free Chip Scale Packages

2003 ◽  
Author(s):  
Arun Gowda ◽  
Anthony Primavera ◽  
K. Srihari
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Printed Circuit ◽  
Free Solder ◽  
The Individual ◽  
Component Assembly ◽  
Free Area

The implementation of lead-free solder into an electronics assembly process necessitates the reassessment of the individual factors involved in component attachment and rework. A component assembly undergoes multiple thermal cycles during rework. With the use of lead-free solder, the assemblies are subjected to higher assembly and rework temperatures than those required for eutectic tin-lead assemblies. The rework of lead-free area array components involves the removal of defective component, preparation of the printed circuit board attachment pad (site redressing), solder paste replenishment or flux deposition, and component placement and reflow. This paper primarily focuses on the site redressing aspect of lead-free rework, followed by the development of rework processes for lead-free chip scale packages utilizing the knowledge gained in the site redressing studies.

Unique Failure Modes from use of Sn-Pb and Lead-Free (mixed metallurgies) in PCB Assembly: Case Study

2005 ◽  
Author(s):  
Frank Toth ◽  
Gary F. Shade
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Circuit Board ◽  
Lead Free ◽  
Printed Circuit ◽  
Pcb Assembly ◽  
New Process ◽  
Solder Pastes

Abstract Printed Circuit Board (PCB) assemblies are moving toward lead-free (LF) alloys and away from the traditional Sn-Pb alloy [1]. This change is creating new and unique failure modes as the process adapts to accommodate the higher temperatures of the new process [2]. In addition, mis-processed lots are more likely due to the complexity of assembling a mix of Sn-Pb and leadfree solders, components, PCBs, solder pastes, and fluxes. This case study helps to highlight the challenge and provides an example of what can happen, how to detect it, and how the defects can cause reliability failures.

Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board

2000 ◽  
Author(s):  
John H. Lau ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Shear Stress ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Shear Creep ◽  
Printed Circuit ◽  
Chip Scale Package ◽  
Free Solder

Abstract In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt%Sn-3.5wt%Ag and 100wt%In. The 62wt%Sn-36wt%Pb-2wt%Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP solder joint reliability are investigated.

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