Unique Failure Modes from use of Sn-Pb and Lead-Free (mixed metallurgies) in PCB Assembly: Case Study

Author(s):  
Frank Toth ◽  
Gary F. Shade

Abstract Printed Circuit Board (PCB) assemblies are moving toward lead-free (LF) alloys and away from the traditional Sn-Pb alloy [1]. This change is creating new and unique failure modes as the process adapts to accommodate the higher temperatures of the new process [2]. In addition, mis-processed lots are more likely due to the complexity of assembling a mix of Sn-Pb and leadfree solders, components, PCBs, solder pastes, and fluxes. This case study helps to highlight the challenge and provides an example of what can happen, how to detect it, and how the defects can cause reliability failures.

2022 ◽  
Vol 12 (2) ◽  
pp. 640
Author(s):  
Cher-Ming Tan ◽  
Hsiao-Hi Chen ◽  
Jing-Ping Wu ◽  
Vivek Sangwan ◽  
Kun-Yen Tsai ◽  
...  

A printed circuit board (PCB) is an essential element for practical circuit applications and its failure can inflict large financial costs and even safety concerns, especially if the PCB failure occurs prematurely and unexpectedly. Understanding the failure modes and even the failure mechanisms of a PCB failure are not sufficient to ensure the same failure will not occur again in subsequent operations with different batches of PCBs. The identification of the root cause is crucial to prevent the reoccurrence of the same failure. In this work, a step-by-step approach from customer returned and inventory reproduced boards to the root cause identification is described for an actual industry case where the failure is a PCB burn-out. The failure mechanism is found to be a conductive anodic filament (CAF) even though the PCB is CAF-resistant. The root cause is due to PCB de-penalization. A reliability verification to assure the effectiveness of the corrective action according to the identified root cause is shown to complete the case study. This work shows that a CAF-resistant PCB does not necessarily guarantee no CAF and PCB processes can render its CAF resistance ineffective.


Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.


Author(s):  
Jun-Xian Fu ◽  
Shukri Souri ◽  
James S. Harris

Abstract Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.


Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.


2021 ◽  
Author(s):  
Carles Ribas Tugores ◽  
Gerald Birngruber ◽  
Jürgen Fluch ◽  
Angelika Swatek ◽  
Gerald Schweiger

2008 ◽  
Vol 20 (2) ◽  
pp. 30-38 ◽  
Author(s):  
Jeffery C.C. Lo ◽  
B.F. Jia ◽  
Z. Liu ◽  
J. Zhu ◽  
S.W. Ricky Lee

2014 ◽  
Vol 874 ◽  
pp. 139-143 ◽  
Author(s):  
Jacek Pietraszek ◽  
Aneta Gądek-Moszczak ◽  
Tomasz Toruński

PartnerTech provides printed circuit board (PCB) assembly on request. Wired elements are assembled in through-hole technology and soldered on the wave soldering machine. The PCB with inserted elements is passed across the pumped wave of melted solder. Typically this process is accompanied by some class of defects like cracks, cavities, wrong solder thickness and poor conductor. In PartnerTech Ltd. another type of defects was observed: dispersion of small droplets of solder around holes. Quality assurance department plans to optimize the process in order to reduce the number of defects. In the first stage, it was necessary to develop a methodology for counting defects. This paper presents experimental design and analysis related to this project.


Manufacturing ◽  
2002 ◽  
Author(s):  
J. Cecil ◽  
A. Kanchanapiboon

This paper presents a framework for supporting virtual prototyping related activities in the domain of printed circuit board (PCB) assembly. The focus of discussion is restricted to Surface Mount Technology (SMT) based processes only. In general, Virtual Prototyping enables the conceptualization, evaluation and validation of proposed ideas, plans and solutions. Using a virtual prototyping framework, cross functional evaluation and analysis can be facilitated where designers, manufacturing engineers, testing and other life-cycle team members can communicate effectively as well as identify and eliminate problems, which may arise later in the downstream manufacturing and testing activities.


Author(s):  
Todd Embree ◽  
Deassy Novita ◽  
Gary Long ◽  
Satish Parupalli

The continual drive toward smaller second level interconnect dimensions, along with the introduction of Halogen-Free circuit board materials and increased process temperatures of Lead-Free solders, have all contributed to a more frequent occurrence of Pad Crater damage in circuit board materials during manufacturing and test processes. This paper addresses the methodology and test data of some common industry methods used to evaluate Pad Crater strength in circuit board materials. Pad Crater test data is highly sensitive to sample design; as a result a discussion of sample design criteria is also included.


Sign in / Sign up

Export Citation Format

Share Document