Abstract
With IP traffic increasing by 10-fold over the last decade, together with limitation and cost increase due to shrinking semiconductor nodes have led to requiring technological breakthrough in the packaging of semiconductor devices especially those used in high performance computing (HPC).This increase in IP traffic has led to requirement for higher data speed transmission in these devices, and consequently packaging technologies that enable those solutions such as 2.5D packaging utilizing silicon interposers. Furthermore, in recent years, increasing number of dies are placed in a single package for these devices thereby making the size of silicon interposers larger. Thus, the design of organic substrates used in these devices, are also becoming ever complex often with multiple layers with long trace lengths for routing increased number of IOs and allowing for power and signal control management. In order to facilitate the high speed data transmission requirement with longer trace lengths, stable low insertion loss design of organic substrates are becoming significantly important even when devices are exposed at elevated humidity or higher temperatures due to surrounding environment or from dies heating. Additionally, as silicon interposers are increasing in size, preventing stress build-up, which can cause cracking between the interposer and the organic substrate, is also becoming paramount. These requirements have led to innovative materials to be developed to enable organic substrates to have these properties. In this paper, we present a new dielectric build-up material for use in advanced organic substrates, by combining newly developed original resin with existing formulation technology that meet these criteria of enabling lower insertion loss with design that reduces deterioration even at elevated humidity and temperature, and furthermore having high crack resistance during temperature cycle testing.