Improved Capillary Electrophoresis Separation Using a Capillary Bundle

2008 ◽  
Author(s):  
Nam-Trung Nguyen ◽  
Yi Sun ◽  
Yien-Chian Kwok
Keyword(s):  
Capillary Electrophoresis ◽  
Joule Heating ◽  
Heat Dissipation ◽  
Electrical Current ◽  
Electric Resistance ◽  
Separation Channel ◽  
Cross Sectional ◽  
Narrow Channels ◽  
Capillary Bundle ◽  
Separation Columns

Joule heating is an undesirable effect in capillary electrophoresis (CE). The heat generated by the electrical current leads to a temperature gradient along the separation channel and consequently affects the separation quality. Since the heat is inversely proportional to the electric resistance of the separation column, increasing the electric resistance can reduce the effect of Joule heating. Currently, due to the limit of fabrication technique and detection apparatus, the typical dimensions of CE microchannels are in the range of 50 μm to 200 μm. In this paper, we describe the method of reducing the cross-sectional area of the separation channel and increasing the channel’s surface for better heat dissipation. A photonic crystal fiber (PCF) is a bundle of extremely narrow channels, which ideally work as separation columns. The PCF was simply encapsulated in a polymethylmethacrylate (PMMA) microchannel right after a T-shaped injector. CE was simultaneously but independently carried out in 54 narrow capillaries, each capillary with diameter of 3.7 μm. The capillary bundle could sustain high electric field strength up to 1000 V/cm due to efficient heat dissipation, thus faster and enhanced separation was attained.

Thermal and Electrical Transport in Carbon Nanofiber Interconnects

2008 ◽  
Author(s):  
Tsutomu Saito ◽  
Hirohiko Kitsuki ◽  
Makoto Suzuki ◽  
Toshishige Yamada ◽  
Drazen Fabris ◽  
...  
Keyword(s):  
Heat Transport ◽  
Carbon Nanofibers ◽  
Joule Heating ◽  
Current Density ◽  
Electrical Transport ◽  
Heat Dissipation ◽  
Carbon Nanofiber ◽  
Transport Model ◽  
High Current ◽  
Current Stress

We study reliability of carbon nanofibers (CNFs) under high-current stress by examining CNF breakdown on four different configurations, suspended or supported, with/without tungsten deposition. The suspended results are consistently explained with a heat transport model taking into account Joule heating and heat dissipation along the CNF, while supported cases show a consistently larger current density just before breakdown, reflecting effective heat dissipation to the substrate.

Numerical simulation of Joule heating effect on sample band transport in capillary electrophoresis

2006 ◽  
Vol 561 (1-2) ◽  
pp. 138-149 ◽  
Author(s):  
G.Y. Tang ◽  
C. Yang ◽  
H.Q. Gong ◽  
J.C. Chai ◽  
Y.C. Lam
Keyword(s):  
Numerical Simulation ◽  
Capillary Electrophoresis ◽  
Joule Heating ◽  
Heating Effect ◽  
Joule Heating Effect

Effect of TSV Joule Heating on Device Performance

2013 ◽  
Author(s):  
Fahad Mirza ◽  
Gaurang Naware ◽  
Thiagarajan Raman ◽  
Ankur Jain ◽  
Dereje Agonafer
Keyword(s):  
Joule Heating ◽  
Heat Dissipation ◽  
Form Factors ◽  
Signal Propagation ◽  
Junction Temperature ◽  
Electrical Performance ◽  
Device Performance ◽  
Base Line ◽  
Heat Current ◽  
Current Path

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs. TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

scholarly journals Evaluation of the quality of layers applied by LDT laser metal deposition

2018 ◽  
Vol 19 (6) ◽  
pp. 591-596
Author(s):  
Andrzej Mazurkiewicz ◽  
Andrzej Poprzeczka
Keyword(s):  
Heat Affected Zone ◽  
Heat Dissipation ◽  
Scanning Speed ◽  
Processing Parameters ◽  
Metal Deposition ◽  
Laser Metal Deposition ◽  
Cross Sectional ◽  
Weld Overlay ◽  
The Cross

The article presents the results of a study of C45 carbon steel hardfacing using laser metal deposition with Stellit Co-21 powder. The microstructure of the cross-section of samples prepared with different scanning speed and the amount of used powder at constant laser power was observed. Analyzing the cross-sectional areas of the samples, it was found that, at specific production parameters, cracks occur in weld overlay, which should be associated with the amount of heat supplied and discharged, especially at the unheated basis.This may be confirmed by the presence of deposits of weakly branched dendrites in the microstructure, which should be related to the directional heat dissipation process and rapid directional crystallization. It is possible to regulate these phenomena by selecting appropriate processing parameters. The microstructure analysis of cross-sectional areas of samples after hardfacing using LDT technique indicates good metallurgical quality of the deposit with a small heat affected zone of about 660÷760m. The microhardness measurements on the sample cross-sections indicated a wide micohardness distribution ranging from 510HV1 in the weld overlay, about 410HV1 in the heat affected zone, to 270HV1 in the C45 steel base.

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