High-performance proximity effect correction for sub-70 nm design rule system on chip devices in 100 kV electron projection lithography

2003 ◽  
Vol 21 (6) ◽  
pp. 2663 ◽  
Author(s):  
Kozo Ogino ◽  
Hiromi Hoshino ◽  
Yasuhide Machida ◽  
Morimi Osawa ◽  
Hiroshi Arimoto ◽  
...  
Keyword(s):  
Proximity Effect ◽  
High Performance ◽  
System On Chip ◽  
Design Rule ◽  
Projection Lithography ◽  
On Chip ◽  
Rule System ◽  
Proximity Effect Correction

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture

2021 ◽  
pp. 1-12
Author(s):  
Arun Prasath Raveendran ◽  
Jafar A. Alzubi ◽  
Ramesh Sekaran ◽  
Manikandan Ramachandran
Keyword(s):  
High Performance ◽  
Standard Technique ◽  
System On Chip ◽  
Mixed Integer ◽  
Multiprocessor System ◽  
Compound System ◽  
Available Bandwidth ◽  
Mip Model ◽  
Fpga Chip ◽  
On Chip

This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

Tofu Interconnect 2: System-on-Chip Integration of High-Performance Interconnect

2014 ◽  
pp. 498-507 ◽  
Author(s):  
Yuichiro Ajima ◽  
Tomohiro Inoue ◽  
Shinya Hiramoto ◽  
Shunji Uno ◽  
Shinji Sumimoto ◽  
...  
Keyword(s):  
High Performance ◽  
System On Chip ◽  
On Chip

High-Speed Proximity Effect Correction System for Electron-Beam Projection Lithography by Cluster Processing

2003 ◽  
Vol 42 (Part 1, No. 6B) ◽  
pp. 3827-3832 ◽  
Author(s):  
Kozo Ogino ◽  
Hiromi Hoshino ◽  
Yasuhide Machida ◽  
Morimi Osawa ◽  
Hiroshi Arimoto ◽  
...  
Keyword(s):  
Electron Beam ◽  
Proximity Effect ◽  
High Speed ◽  
Projection Lithography ◽  
Beam Projection ◽  
Proximity Effect Correction ◽  
Correction System

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

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