scholarly journals Low-cost and High-speed Nanophotonic Integrated Circuits for Access Networks

2019 ◽  
Author(s):  
Yuqing Jiao ◽  
Jos van der Tol ◽  
Weiming Yao ◽  
Kevin Williams
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Access Networks

scholarly journals In-Plane Monolithic Integration of Scaled III-V Photonic Devices

2021 ◽  
Vol 11 (4) ◽  
pp. 1887
Author(s):  
Markus Scherrer ◽  
Noelia Vico Triviño ◽  
Svenja Mauthe ◽  
Preksha Tiwari ◽  
Heinz Schmid ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Photonic Devices ◽  
Monolithic Integration ◽  
Light Emitters ◽  
Fully Integrated ◽  
Large Lattice ◽  
Hybrid Iii ◽  
Gain Material

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.

Bipolar device technology challenge and opportunity

1985 ◽  
Vol 63 (6) ◽  
pp. 683-692 ◽  
Author(s):  
H. D. Barber
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Chemical Vapor ◽  
Low Noise ◽  
Isolation Techniques ◽  
Propagation Delays ◽  
Technological Barriers ◽  
On Chip ◽  
Bipolar Device

Silicon bipolar device technologies provided 65% of the world's integrated circuits in 1983. Where low noise, high current, low or high voltage, high speed or low cost are required, bipolar technologies are used. This paper will review the present status of bipolar device technologies, which make possible 100-ps gate-propagation delays, 150-μm2 gate areas, 1-GHz bandwidth amplifiers, on-chip control of over 1-A, 350-V operation, 14-GHz fT's and 10-ns. analogue-to-8-bit digital conversion. These devices are realized because of advances in isolation techniques, chemical-vapor deposition, photolithography, diffusion, ion implantation, conductor–contact interconnection technology, etching processes, and materials preparation. This paper will discuss some of the fundamental problems, modelling difficulties, and technological barriers that will impact the future development of bipolar integrated circuits.

scholarly journals Architecture and implementation of a high frame-rate stereo vision system

2021 ◽  
Author(s):  
Jamin Islam
Keyword(s):  
Integrated Circuits ◽  
Stereo Vision ◽  
High Speed ◽  
Vision System ◽  
Low Cost ◽  
Cost Effective ◽  
Frame Rate ◽  
Superior Performance ◽  
High Frame Rate ◽  
Stereo Vision System

For the purpose of autonomous satellite grasping, a high-speed, low-cost stereo vision system is required with high accuracy. This type of system must be able to detect an object and estimate its range. Hardware solutions are often chosen over software solutions, which tend to be too slow for high frame-rate applications. Designs utilizing field programmable gate arrays (FPGAs) provide flexibility and are cost effective versus solutions that provide similar performance (i.e., Application Specific Integrated Circuits). This thesis presents the architecture and implementation of a high frame-rate stereo vision system based on an FPGA platform. The system acquires stereo images, performs stereo rectification and generates disparity estimates at frame-rates close to 100 fpSi and on a large-enough FPGA, it can process 200 fps. The implementation presents novelties in performance and in the choice of the algorithm implemented. It achieves superior performance to existing systems that estimate scene depth. Furthermore, it demonstrates equivalent accuracy to software implementations of the dynamic programming maximum likelihood stereo correspondence algorithm.

Gallium arsenide electronics in the marketplace

1992 ◽  
Vol 70 (10-11) ◽  
pp. 943-945
Author(s):  
Paul R. Jay.
Keyword(s):  
Gallium Arsenide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Logic Gates ◽  
Process Technology ◽  
Maximum Benefit ◽  
Technological Developments

The last few years have seen a significant emergence of real product applications using gallium arsenide metal semi-conductor field effect transistor technology. These applications range from large volume consumer markets based on small low-cost GaAs integrated circuits to high-end supercomputer products using very large scale integrated GaAs chips containing up to 50 000 logic gates. This situation represents substantial advances in many areas: materials technology, device and integrated circuit process technology, packaging and high speed testing, as well as appropriate system design to obtain maximum benefit from the GaAs technology. This paper reviews some recent commercial successes, and considers commonalities existing between them in the context of recent technological developments.

scholarly journals Advances in Low Cost Silver-Containing Thick Film Conductors

1981 ◽  
Vol 9 (1) ◽  
pp. 67-85 ◽  
Author(s):  
Barry E. Taylor ◽  
John J. Felten ◽  
Samuel J. Horowitz ◽  
John R. Larry ◽  
Richard M. Rosenberg
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Thick Film ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
High Volume ◽  
Film Material ◽  
Advantages And Disadvantages ◽  
Thick Film Technology

Extensive use of thick film materials to manufacture resistor networks and hybrid integrated circuits has come about because of economic, processing and functional advantages over other technologies in the high volume production of miniaturized circuits. Inherent in the adoption of thick film technology for increasingly diverse applications has been the ability of thick film material suppliers to provide progressive performance improvements at lower cost concurrent with circuit manufacturer's needs. Since the first major commercial thick film adoption in the early sixties, when IBM adopted platinum gold conductors and palladium silver resistors in their 360 computers, rapid technological advances over the last decade have produced an increasing variety of hybrid circuits and networks. The wide adoption of thick film technology in all segments of the electronic industry has placed increasing demands on performance and processing latitude. This paper outlines the development of low cost silver-bearing conductors and describes the evolution of technology improvements to present day systems. The initial segment reviews the deficiencies of early Pd/Ag conductors, particularly solder leach resistance and degradation of soldered adhesion following high temperature storage, and focuses on the first Pd/Ag system which overcame these problems. Extension of this technology and subsequent improvements in both binders and vehicles to fulfill adhesion requirements to Al2O3substrates of varying chemistries and to meet demands for high speed printing are also described. The second segment gives an overview of the present understanding of thick film conductor composites from a mechanistic point of view. The various types of binder systems commonly employed in conductors are discussed in terms of how they effect a bond between the sintered metal and the substrate, and the advantages and disadvantages of each type. Metallurgical aspects of conductor/solder connections are considered and their effects on bond reliability following exposure to high temperature discussed. Rheological considerations of paste design are presented and related to printing performance. The final segment focuses on newer low cost, high performance material systems that have evolved over the past two years. The technologies of each system are reviewed in terms of metallurgy, binder and vehicle. Important functional properties are presented to illustrate cost/performance tradeoffs. Special emphasis is given to recently developed high Ag containing conductors which have outstanding soldered adhesion even after 1000 hours of storage at 150℃.

scholarly journals A 1GHz Low-cost, Ultra Low-noise Preamplifier

2020 ◽  
Vol 11 ◽  
pp. 120-126
Author(s):  
J. Chatzakis ◽  
S. Hassan ◽  
E. Clark ◽  
M. Tatarakis
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Low Noise ◽  
Silicon Photomultipliers ◽  
Low Frequencies ◽  
Measurement Systems ◽  
Speed Measurement ◽  
Ultra Low Noise ◽  
Low Noise Preamplifier

A high quality, compact 1GHz preamplifier suitable for operation in conjunction with micro channelplates (MCP) and silicon Photomultipliers (SiPM), that is comprised of two integrated circuits is described inthis paper. The amplifier requires no adjustment and has a flat response from low frequencies and adequatebandwidth for high speed measurement systems.

scholarly journals Architecture and implementation of a high frame-rate stereo vision system

2021 ◽  
Author(s):  
Jamin Islam
Keyword(s):  
Integrated Circuits ◽  
Stereo Vision ◽  
High Speed ◽  
Vision System ◽  
Low Cost ◽  
Cost Effective ◽  
Frame Rate ◽  
Superior Performance ◽  
High Frame Rate ◽  
Stereo Vision System

For the purpose of autonomous satellite grasping, a high-speed, low-cost stereo vision system is required with high accuracy. This type of system must be able to detect an object and estimate its range. Hardware solutions are often chosen over software solutions, which tend to be too slow for high frame-rate applications. Designs utilizing field programmable gate arrays (FPGAs) provide flexibility and are cost effective versus solutions that provide similar performance (i.e., Application Specific Integrated Circuits). This thesis presents the architecture and implementation of a high frame-rate stereo vision system based on an FPGA platform. The system acquires stereo images, performs stereo rectification and generates disparity estimates at frame-rates close to 100 fpSi and on a large-enough FPGA, it can process 200 fps. The implementation presents novelties in performance and in the choice of the algorithm implemented. It achieves superior performance to existing systems that estimate scene depth. Furthermore, it demonstrates equivalent accuracy to software implementations of the dynamic programming maximum likelihood stereo correspondence algorithm.

scholarly journals Design a 900 Hybrid Feed Square Patch Stacked Antenna at 3GHz

2021 ◽  
Vol 10 (3) ◽  
pp. 201-205
Author(s):  
V. Saidulu
Keyword(s):  
Integrated Circuits ◽  
Glass Substrate ◽  
High Speed ◽  
Low Cost ◽  
Satellite Communications ◽  
Microstrip Antennas ◽  
Experimental Result ◽  
Microwave Antenna ◽  
Cross Polarization ◽  
Low Volume

Microstrip antennas find wide applications in high-speed vehicles, and missiles, tanks, satellite communications etc. The main advantage of these antennas over conventional microwave antenna are lightweight, low volume, low cost, planar structure and compatibility with integrated circuits. The present paper deals with the design and development of 90o hybrid feed square patch stacked antenna. The design of square patch and 900 hybrid feed has been carried out at frequency of 3 GHz on epoxy glass substrate, the radiation pattern of the square patch has been experimentally studied. The effect of stacked patches placed above the square patch has been studied experimentally for different cases like 1,2,3 and 4 stacked patches placed one above other above the driven square patch. From the experimental result it has been found that performance of the case of 1 + 2 (one driven element and two parasitic element) is optimum with bandwidth of 16 % and VSWR 1.42 the performance degrades the no of practical elements is increased that is for case 1 + 3 and 1 + 4 etc., The performance of 1 + 2 case of also found to be superior to the performance 1+ 0 and 1+1 cases experimentally studied, also been carried out for cross Polarization and co – polarization.

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

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