IMPLEMENTATION OF AN RF CMOS QUADRATURE LC VOLTAGE-CONTROLLED OSCILLATOR BASED ON THE SWITCHED TAIL TRANSISTOR TOPOLOGY

2010 ◽  
Vol 19 (05) ◽  
pp. 931-937
Author(s):  
APINUNT THANACHAYANONT ◽  
MONAI KRAIRIKSH
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Coupling Mechanism ◽  
Voltage Controlled Oscillator ◽  
Rf Cmos ◽  
Power Supply Voltage ◽  
Switch Capacitor ◽  
Measurement Results ◽  
Offset Frequency ◽  
Signal Swing

This paper describes the design and implementation of an RF CMOS quadrature LC voltage-controlled oscillator in a 0.35 μm technology. The proposed oscillator employs the switched tail transistor topology and differential switch capacitor tuning to achieve low phase noise operation. A modified series coupling mechanism is used for quadrature signal generation with wide output signal swing. The oscillator core circuit was designed to operate with a 2.5 V power supply voltage with a 4 mA total supply current. Measurement results showed that the prototype oscillator could achieve a nominal oscillation frequency of 2.2 GHz with -110 dBc/Hz phase noise at 1 MHz offset frequency.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Low Phase Noise Voltage Controlled Oscillator Using Cascode and Current-Reuse Techniques for Radio Frequency Circuits

2013 ◽  
Vol 479-480 ◽  
pp. 513-516
Author(s):  
Shuo Chang Hsu ◽  
Meng Ting Hsu ◽  
Yu Tuan Hsu
Keyword(s):  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Building Blocks ◽  
Voltage Controlled Oscillator ◽  
Ieee 802.11A ◽  
Current Reuse ◽  
Chip Fabrication ◽  
Offset Frequency ◽  
Low Phase Noise

The voltage-controlled-oscillator (VCO) is one of the most important building blocks in the system. The chip fabrication of VCO is made by TSMC 0.18μm 1P6M CMOS standard process. The chip presents a low power and low phase noise for IEEE 802.11a applications, the PMOS casecode and current-reuse cross-couple technology are designed to improve phase noise and reduce power. The measured results of phase noise is-120.87 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.05 GHz, and operates frequency from 5.04 GHz to 5.895 GHz with a tuning range of 17.14%. Under supply voltage 1.65V, the core power dissipation is 4.05 mW.

A Low Phase Noise Fully Monolithic 6 GHz Differential Coupled NMOS LC-VCO

Frequenz ◽  
2016 ◽  
Vol 70 (1-2) ◽  
Author(s):  
Dorra Mellouli Moalla ◽  
David Cordeau ◽  
Hassene Mnif ◽  
Jean-Marie Paillot ◽  
Mourad Loulou
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Power Supply Voltage ◽  
Worst Case ◽  
Resistive Network ◽  
Phased Antenna Array ◽  
Free Running ◽  
Phase Progression ◽  
Low Phase Noise

AbstractA fully monolithic 6 GHz low-phase noise Voltage-Controlled-Oscillator (VCO) is presented in this paper. It consists in two LC-NMOS differential VCOs coupled through a resistive network and is implemented on a 0.25 µm BiCMOS SiGe process. This proposed integrated VCO can be used also for phased-array applications to steer the beam over the entire spatial range. In this case, the radiation pattern of the phased antenna array is steered in a particular direction by establishing a constant phase progression in the oscillator chain which can be obtained by detuning the free-running frequencies of the two oscillators in the array. At 2.5 V power supply voltage and a power dissipation of 62.5 mW, the coupled VCO array features a measured worst case phase noise of

Design of 5 GHz low-power CMOS LC VCO based on complementary cross-coupled topology with modified tail current-shaping technique

2014 ◽  
Vol 6 (6) ◽  
pp. 573-580 ◽  
Author(s):  
Meng-Ting Hsu ◽  
Po-Hung Chen ◽  
Yao-Yen Lee
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Measurement Results ◽  
Low Power Cmos ◽  
5 Ghz ◽  
Low Phase Noise ◽  
Manufacture Company

In this paper, a low-power CMOS LC voltage-controlled oscillator (VCO) with body-biasing and low-phase noise with Q-enhancement techniques is presented. A self-body biased circuit is introduced that can reduce power consumption. Some derivations of the Q-enhancement and how to improve the phase noise of the circuit are also discussed. This chip is implemented by the Taiwan Semiconductor Manufacture Company 0.18 µm 1P6M process. The measurement results exhibit a tuning range of 14.7% from 4.92 to 5.7 GHz at a supply voltage of 1.4 V. The power consumption of the core circuit and figure of merit are 2.5 mW and −188.6 dBc/Hz. The phase noise is −118 dBc/Hz@1 MHz at an operation frequency of 4.94 GHz.

A Very Low Power Quadrature VCO with Modified Current-Reuse and Back-Gate Coupling Topology

2017 ◽  
Vol 26 (11) ◽  
pp. 1750184 ◽  
Author(s):  
Qiuzhen Wan ◽  
Jun Dong ◽  
Hui Zhou ◽  
Fei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Current Reuse ◽  
Quadrature Vco ◽  
In Series

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

scholarly journals A Bandwidth-Enhanced Differential LC-Voltage Controlled Oscillator (LC-VCO) and Superharmonic Coupled Quadrature VCO for K-Band Applications

Electronics ◽  
2018 ◽  
Vol 7 (8) ◽  
pp. 127 ◽  
Author(s):  
Farman Ullah ◽  
Yu Liu ◽  
Zhiqiang Li ◽  
Xiaosong Wang ◽  
Muhammad Sarfraz ◽  
...  
Keyword(s):  
Phase Noise ◽  
High Performance ◽  
Tuning Range ◽  
Voltage Controlled Oscillator ◽  
Sige Bicmos ◽  
Quadrature Vco ◽  
Free Running ◽  
A New Technique ◽  
Offset Frequency ◽  
Lc Vco

A novel varactor circuit exhibiting a wider tuning range and a new technique for quadrature coupling of LC-Voltage Controlled Oscillator (LC-VCO) is presented and validated on a 25 GHz oscillator. The proposed varactor circuit employs distribute-biased parallel varactors with a series inductor connected at both ends of the varactor bank to extend the tuning range of the oscillator. Similarly, the quadrature coupling is accomplished by employing the 2nd harmonic, explicitly generated in the stand-alone free-running differential oscillator using frequency doubler. As an example, the Differential VCO (DVCO) is tunable between 20 GHz and 31 GHz and exhibits the best Phase Noise (PN) of −100 dBc/Hz at 1 MHz offset frequency. Similarly, the Quadrature VCO (QVCO) covers 42% tuning bandwidth around 25 GHz oscillation frequency, which is significantly wider than other state-of-the-art VCOs at comparable frequencies. In addition, all the oscillators are designed in class-C to further improve their performances both in term of low power and low phase noise. The presented oscillators are designed using high-performance SiGe HBTs of the GlobalFoundries (GFs) 130 nm SiGe BiCMOS 8HP process. The presented DVCO and QVCO draw currents of approximately 10 mA and 21 mA, respectively from a 1.2 V supply.

scholarly journals A LOW PHASE NOISE, POWER EFFICIENT VOLTAGE CONTROLLED OSCILLATOR USING 0.18-μM CMOS TECHNOLOGY

2014 ◽  
pp. 256-259
Author(s):  
AJIT SAMASGIKAR
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Noise Power ◽  
Voltage Controlled Oscillator ◽  
Power Efficient ◽  
Sustained Oscillations ◽  
Low Phase Noise

A low phase noise, power efficient VCO using UMC 0.18μm CMOS technology has been proposed in this paper. The proposed VCO has a tuning range of 9.71GHz to 9.9GHz, with a phase noise of -79.88 dBc/Hz @ 600kHz offset. The Vtune ranging between 1V - 1.5V generates sustained oscillations. The maximum power consumption of the VCO is 11.9mW using a supply voltage of 1.8V with ±10% variation.

scholarly journals DESIGN AND INVESTIGATION OF 65 NM RF CMOS TECHNOLOGY LC-VCO’S / AUKŠTADAŽNIŲ, 65 NM KMOP TECHNOLOGIJOS, LC ĮTAMPA VALDOMŲ GENERATORIŲ PROJEKTAVIMAS IR TYRIMAS

2014 ◽  
Vol 6 (2) ◽  
pp. 198-201 ◽  
Author(s):  
Vytautas Mačaitis ◽  
Vaidotas Barzdėnas
Keyword(s):  
Power Dissipation ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Rf Cmos ◽  
Voltage Controlled Oscillators ◽  
Capacitor Array ◽  
Layout Area ◽  
Offset Frequency

In this paper, two LC Voltage-Controlled Oscillators (LC-LC-VCO1 and LC-VCO2) are designed using TSMC 65 nm LP/MS/RF CMOS technology. Two arrays, one of which is a 6-bit capacitor array and the other – an array of MOS varactors, provide a wide LC-VCO frequency tuning range. Post-layout simulation results unveiled that at 1.8 V supply voltage the tuning range of LC-VCO1 spans from 5.17 GHz to 6.76 GHz and for LC-VCO2 the range spans from 6.33 GHz to 8.08 GHz. The phase noise at 1 MHz offset frequency is about −123.1 dBc/Hz for LC-VCO1 and −121.6 dBc/Hz for LC-VCO2. The power dissipation at maximum carrier is 30.47 mW for LC-VCO1 and 30.5 mW for LC-VCO2. The layout area is 285×335 μm and 255×305 μm, respectively for LC-VCO1 and LC-VCO2. Straipsnyje nagrinėjami ir projektuojami LC įtampa valdomi generatoriai (LC-ĮVG), plačiai taikomi šiuolaikiniuose daugiastandarčiuose ir daugiajuosčiuose siųstuvuose-imtuvuose. Naudojant TSMC kompanijos 65 nm LP/MS/RF KMOP inte­grinių grandynų gamybos technologiją suprojektuoti ir išanalizuoti du skirtingų dažnio diapazonų LC-ĮVG. Generuojamas dažnis yra valdomas dviem būdais, t. y. galimas apytikslis bei tikslus dažnio nustatymas. Norint apytiksliai nustatyti dažnį naudojamas 6 bitais skaitmeniškai valdomas perjungiamų kondensatorių blokas, o norint tiksliai parinkti valdymą – NMOP varaktorių blokas. Kompiuterinio modeliavimo metu gauti tokie pagrindiniai LC-ĮVG parametrai: valdomo dažnio diapazonas – nuo 5,17 GHz iki 6,76 GHz (LC-ĮVG1) ir nuo 6,33 GHz iki 8,08 GHz (LC-ĮVG2); fazinis triukšmas, esant 1 MHz poslinkio dažniui ir maksimaliam nešlio dažniui: –123,1 dBc/Hz (LC-ĮVG1) ir –121,6 dBc/Hz (LC-ĮVG2); vartojamoji galia, esant maksimaliam nešlio dažniui: –30,47 mW (LC-ĮVG1) ir 30,5 mW (LC-ĮVG2). Suprojektuotų LC-ĮVG1 ir LC-ĮVG2 topologijų plotas yra atitinkamai lygus 0,078 mm2 ir 0,096 mm2.

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